-------------------------------------------------------------------------------- -- File Name: idt72t54242.vhd -------------------------------------------------------------------------------- -- Copyright (C) 2005 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 S.Gmitrovic 05 Aug 31 Initial release -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: IDT_FIFO -- Technology: CMOS -- Part: IDT72T54242 -- Description: 32,768x10x4/16,384x20x2 QUAD/DUAL TeraSync DDR/SDR FIFO -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL; ENTITY idt72t54242 IS GENERIC ( -- tipd delays: interconnect path delays tipd_D0 : VitalDelayType01 := VitalZeroDelay01; tipd_D1 : VitalDelayType01 := VitalZeroDelay01; tipd_D2 : VitalDelayType01 := VitalZeroDelay01; tipd_D3 : VitalDelayType01 := VitalZeroDelay01; tipd_D4 : VitalDelayType01 := VitalZeroDelay01; tipd_D5 : VitalDelayType01 := VitalZeroDelay01; tipd_D6 : VitalDelayType01 := VitalZeroDelay01; tipd_D7 : VitalDelayType01 := VitalZeroDelay01; tipd_D8 : VitalDelayType01 := VitalZeroDelay01; tipd_D9 : VitalDelayType01 := VitalZeroDelay01; tipd_D10 : VitalDelayType01 := VitalZeroDelay01; tipd_D11 : VitalDelayType01 := VitalZeroDelay01; tipd_D12 : VitalDelayType01 := VitalZeroDelay01; tipd_D13 : VitalDelayType01 := VitalZeroDelay01; tipd_D14 : VitalDelayType01 := VitalZeroDelay01; tipd_D15 : VitalDelayType01 := VitalZeroDelay01; tipd_D16 : VitalDelayType01 := VitalZeroDelay01; tipd_D17 : VitalDelayType01 := VitalZeroDelay01; tipd_D18 : VitalDelayType01 := VitalZeroDelay01; tipd_D19 : VitalDelayType01 := VitalZeroDelay01; tipd_D20 : VitalDelayType01 := VitalZeroDelay01; tipd_D21 : VitalDelayType01 := VitalZeroDelay01; tipd_D22 : VitalDelayType01 := VitalZeroDelay01; tipd_D23 : VitalDelayType01 := VitalZeroDelay01; tipd_D24 : VitalDelayType01 := VitalZeroDelay01; tipd_D25 : VitalDelayType01 := VitalZeroDelay01; tipd_D26 : VitalDelayType01 := VitalZeroDelay01; tipd_D27 : VitalDelayType01 := VitalZeroDelay01; tipd_D28 : VitalDelayType01 := VitalZeroDelay01; tipd_D29 : VitalDelayType01 := VitalZeroDelay01; tipd_D30 : VitalDelayType01 := VitalZeroDelay01; tipd_D31 : VitalDelayType01 := VitalZeroDelay01; tipd_D32 : VitalDelayType01 := VitalZeroDelay01; tipd_D33 : VitalDelayType01 := VitalZeroDelay01; tipd_D34 : VitalDelayType01 := VitalZeroDelay01; tipd_D35 : VitalDelayType01 := VitalZeroDelay01; tipd_D36 : VitalDelayType01 := VitalZeroDelay01; tipd_D37 : VitalDelayType01 := VitalZeroDelay01; tipd_D38 : VitalDelayType01 := VitalZeroDelay01; tipd_D39 : VitalDelayType01 := VitalZeroDelay01; tipd_MD : VitalDelayType01 := VitalZeroDelay01; tipd_FSEL0 : VitalDelayType01 := VitalZeroDelay01; tipd_FSEL1 : VitalDelayType01 := VitalZeroDelay01; tipd_FWFT : VitalDelayType01 := VitalZeroDelay01; tipd_IOSEL : VitalDelayType01 := VitalZeroDelay01; tipd_IW : VitalDelayType01 := VitalZeroDelay01; tipd_PDNeg : VitalDelayType01 := VitalZeroDelay01; tipd_MRSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_OE0Neg : VitalDelayType01 := VitalZeroDelay01; tipd_OE1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_OE2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_OE3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_OW : VitalDelayType01 := VitalZeroDelay01; tipd_PRSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RCLK0 : VitalDelayType01 := VitalZeroDelay01; tipd_RCLK1 : VitalDelayType01 := VitalZeroDelay01; tipd_RCLK2 : VitalDelayType01 := VitalZeroDelay01; tipd_RCLK3 : VitalDelayType01 := VitalZeroDelay01; tipd_RCS0Neg : VitalDelayType01 := VitalZeroDelay01; tipd_RCS1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_RCS2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_RCS3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_REN0Neg : VitalDelayType01 := VitalZeroDelay01; tipd_REN1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_REN2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_REN3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_RDDR : VitalDelayType01 := VitalZeroDelay01; tipd_PFM : VitalDelayType01 := VitalZeroDelay01; tipd_SCLK : VitalDelayType01 := VitalZeroDelay01; tipd_SWENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_SRENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_SI : VitalDelayType01 := VitalZeroDelay01; tipd_WCLK0 : VitalDelayType01 := VitalZeroDelay01; tipd_WCLK1 : VitalDelayType01 := VitalZeroDelay01; tipd_WCLK2 : VitalDelayType01 := VitalZeroDelay01; tipd_WCLK3 : VitalDelayType01 := VitalZeroDelay01; tipd_WCS0Neg : VitalDelayType01 := VitalZeroDelay01; tipd_WCS1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_WCS2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_WCS3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_WEN0Neg : VitalDelayType01 := VitalZeroDelay01; tipd_WEN1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_WEN2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_WEN3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_WDDR : VitalDelayType01 := VitalZeroDelay01; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( D0 : IN std_ulogic := 'U'; D1 : IN std_ulogic := 'U'; D2 : IN std_ulogic := 'U'; D3 : IN std_ulogic := 'U'; D4 : IN std_ulogic := 'U'; D5 : IN std_ulogic := 'U'; D6 : IN std_ulogic := 'U'; D7 : IN std_ulogic := 'U'; D8 : IN std_ulogic := 'U'; D9 : IN std_ulogic := 'U'; D10 : IN std_ulogic := 'U'; D11 : IN std_ulogic := 'U'; D12 : IN std_ulogic := 'U'; D13 : IN std_ulogic := 'U'; D14 : IN std_ulogic := 'U'; D15 : IN std_ulogic := 'U'; D16 : IN std_ulogic := 'U'; D17 : IN std_ulogic := 'U'; D18 : IN std_ulogic := 'U'; D19 : IN std_ulogic := 'U'; D20 : IN std_ulogic := 'U'; D21 : IN std_ulogic := 'U'; D22 : IN std_ulogic := 'U'; D23 : IN std_ulogic := 'U'; D24 : IN std_ulogic := 'U'; D25 : IN std_ulogic := 'U'; D26 : IN std_ulogic := 'U'; D27 : IN std_ulogic := 'U'; D28 : IN std_ulogic := 'U'; D29 : IN std_ulogic := 'U'; D30 : IN std_ulogic := 'U'; D31 : IN std_ulogic := 'U'; D32 : IN std_ulogic := 'U'; D33 : IN std_ulogic := 'U'; D34 : IN std_ulogic := 'U'; D35 : IN std_ulogic := 'U'; D36 : IN std_ulogic := 'U'; D37 : IN std_ulogic := 'U'; D38 : IN std_ulogic := 'U'; D39 : IN std_ulogic := 'U'; Q0 : OUT std_logic := 'U'; Q1 : OUT std_logic := 'U'; Q2 : OUT std_logic := 'U'; Q3 : OUT std_logic := 'U'; Q4 : OUT std_logic := 'U'; Q5 : OUT std_logic := 'U'; Q6 : OUT std_logic := 'U'; Q7 : OUT std_logic := 'U'; Q8 : OUT std_logic := 'U'; Q9 : OUT std_logic := 'U'; Q10 : OUT std_logic := 'U'; Q11 : OUT std_logic := 'U'; Q12 : OUT std_logic := 'U'; Q13 : OUT std_logic := 'U'; Q14 : OUT std_logic := 'U'; Q15 : OUT std_logic := 'U'; Q16 : OUT std_logic := 'U'; Q17 : OUT std_logic := 'U'; Q18 : OUT std_logic := 'U'; Q19 : OUT std_logic := 'U'; Q20 : OUT std_logic := 'U'; Q21 : OUT std_logic := 'U'; Q22 : OUT std_logic := 'U'; Q23 : OUT std_logic := 'U'; Q24 : OUT std_logic := 'U'; Q25 : OUT std_logic := 'U'; Q26 : OUT std_logic := 'U'; Q27 : OUT std_logic := 'U'; Q28 : OUT std_logic := 'U'; Q29 : OUT std_logic := 'U'; Q30 : OUT std_logic := 'U'; Q31 : OUT std_logic := 'U'; Q32 : OUT std_logic := 'U'; Q33 : OUT std_logic := 'U'; Q34 : OUT std_logic := 'U'; Q35 : OUT std_logic := 'U'; Q36 : OUT std_logic := 'U'; Q37 : OUT std_logic := 'U'; Q38 : OUT std_logic := 'U'; Q39 : OUT std_logic := 'U'; MD : IN std_ulogic := 'U'; EF0Neg : OUT std_ulogic := 'U'; EF1Neg : OUT std_ulogic := 'U'; EF2Neg : OUT std_ulogic := 'U'; EF3Neg : OUT std_ulogic := 'U'; ERCLK0 : OUT std_ulogic := 'U'; ERCLK1 : OUT std_ulogic := 'U'; ERCLK2 : OUT std_ulogic := 'U'; ERCLK3 : OUT std_ulogic := 'U'; EREN0Neg : OUT std_ulogic := 'U'; EREN1Neg : OUT std_ulogic := 'U'; EREN2Neg : OUT std_ulogic := 'U'; EREN3Neg : OUT std_ulogic := 'U'; FF0Neg : OUT std_ulogic := 'U'; FF1Neg : OUT std_ulogic := 'U'; FF2Neg : OUT std_ulogic := 'U'; FF3Neg : OUT std_ulogic := 'U'; FSEL0 : IN std_ulogic := 'U'; FSEL1 : IN std_ulogic := 'U'; FWFT : IN std_ulogic := 'U'; IOSEL : IN std_ulogic := 'U'; IW : IN std_ulogic := 'U'; PDNeg : IN std_ulogic := 'U'; MRSNeg : IN std_ulogic := 'U'; OE0Neg : IN std_ulogic := 'U'; OE1Neg : IN std_ulogic := 'U'; OE2Neg : IN std_ulogic := 'U'; OE3Neg : IN std_ulogic := 'U'; OW : IN std_ulogic := 'U'; PAE0Neg : OUT std_ulogic := 'U'; PAE1Neg : OUT std_ulogic := 'U'; PAE2Neg : OUT std_ulogic := 'U'; PAE3Neg : OUT std_ulogic := 'U'; PAF0Neg : OUT std_ulogic := 'U'; PAF1Neg : OUT std_ulogic := 'U'; PAF2Neg : OUT std_ulogic := 'U'; PAF3Neg : OUT std_ulogic := 'U'; PRSNeg : IN std_ulogic := 'U'; RCLK0 : IN std_ulogic := 'U'; RCLK1 : IN std_ulogic := 'U'; RCLK2 : IN std_ulogic := 'U'; RCLK3 : IN std_ulogic := 'U'; RCS0Neg : IN std_ulogic := 'U'; RCS1Neg : IN std_ulogic := 'U'; RCS2Neg : IN std_ulogic := 'U'; RCS3Neg : IN std_ulogic := 'U'; REN0Neg : IN std_ulogic := 'U'; REN1Neg : IN std_ulogic := 'U'; REN2Neg : IN std_ulogic := 'U'; REN3Neg : IN std_ulogic := 'U'; RDDR : IN std_ulogic := 'U'; PFM : IN std_ulogic := 'U'; SCLK : IN std_ulogic := 'U'; SWENNeg : IN std_ulogic := 'U'; SRENNeg : IN std_ulogic := 'U'; SI : IN std_ulogic := 'U'; SDO : OUT std_logic := 'U'; WCLK0 : IN std_ulogic := 'U'; WCLK1 : IN std_ulogic := 'U'; WCLK2 : IN std_ulogic := 'U'; WCLK3 : IN std_ulogic := 'U'; WCS0Neg : IN std_ulogic := 'U'; WCS1Neg : IN std_ulogic := 'U'; WCS2Neg : IN std_ulogic := 'U'; WCS3Neg : IN std_ulogic := 'U'; WEN0Neg : IN std_ulogic := 'U'; WEN1Neg : IN std_ulogic := 'U'; WEN2Neg : IN std_ulogic := 'U'; WEN3Neg : IN std_ulogic := 'U'; WDDR : IN std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of idt72t54242 : ENTITY IS TRUE; END idt72t54242; LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY idt72t54242_onefifo IS GENERIC ( -- tipd delays: interconnect path delays tipd_D0 : VitalDelayType01 := VitalZeroDelay01; tipd_D1 : VitalDelayType01 := VitalZeroDelay01; tipd_D2 : VitalDelayType01 := VitalZeroDelay01; tipd_D3 : VitalDelayType01 := VitalZeroDelay01; tipd_D4 : VitalDelayType01 := VitalZeroDelay01; tipd_D5 : VitalDelayType01 := VitalZeroDelay01; tipd_D6 : VitalDelayType01 := VitalZeroDelay01; tipd_D7 : VitalDelayType01 := VitalZeroDelay01; tipd_D8 : VitalDelayType01 := VitalZeroDelay01; tipd_D9 : VitalDelayType01 := VitalZeroDelay01; tipd_D10 : VitalDelayType01 := VitalZeroDelay01; tipd_D11 : VitalDelayType01 := VitalZeroDelay01; tipd_D12 : VitalDelayType01 := VitalZeroDelay01; tipd_D13 : VitalDelayType01 := VitalZeroDelay01; tipd_D14 : VitalDelayType01 := VitalZeroDelay01; tipd_D15 : VitalDelayType01 := VitalZeroDelay01; tipd_D16 : VitalDelayType01 := VitalZeroDelay01; tipd_D17 : VitalDelayType01 := VitalZeroDelay01; tipd_D18 : VitalDelayType01 := VitalZeroDelay01; tipd_D19 : VitalDelayType01 := VitalZeroDelay01; tipd_MD : VitalDelayType01 := VitalZeroDelay01; tipd_FSEL0 : VitalDelayType01 := VitalZeroDelay01; tipd_FSEL1 : VitalDelayType01 := VitalZeroDelay01; tipd_FWFT : VitalDelayType01 := VitalZeroDelay01; tipd_IOSEL : VitalDelayType01 := VitalZeroDelay01; tipd_IW : VitalDelayType01 := VitalZeroDelay01; tipd_PDNeg : VitalDelayType01 := VitalZeroDelay01; tipd_MRSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; tipd_OW : VitalDelayType01 := VitalZeroDelay01; tipd_PRSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RCLK : VitalDelayType01 := VitalZeroDelay01; tipd_RCSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RDDR : VitalDelayType01 := VitalZeroDelay01; tipd_PFM : VitalDelayType01 := VitalZeroDelay01; tipd_SCLK : VitalDelayType01 := VitalZeroDelay01; tipd_SWENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_SRENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_SI : VitalDelayType01 := VitalZeroDelay01; tipd_WCLK : VitalDelayType01 := VitalZeroDelay01; tipd_WCSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_WENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_WDDR : VitalDelayType01 := VitalZeroDelay01; -- tpd delays -- tA, tRCSLZ, tRCSHZ tASO, tpd_RCLK_Q0 : VitalDelayType01Z := UnitDelay01Z; -- tOLZ, tOHZ, tOE tpd_OENeg_Q0 : VitalDelayType01Z := UnitDelay01Z; -- tPDLZ, tPDHZ tpd_PDNeg_Q0 : VitalDelayType01Z := UnitDelay01Z; -- tRSF tpd_MRSNeg_EFNeg : VitalDelayType01 := UnitDelay01; -- tWFF tpd_WCLK_FFNeg : VitalDelayType01 := UnitDelay01; -- tREF tpd_RCLK_EFNeg : VitalDelayType01 := UnitDelay01; -- tPAFS tpd_WCLK_PAFNeg_sync : VitalDelayType01 := UnitDelay01; -- tPAFA tpd_WCLK_PAFNeg_async : VitalDelayType01 := UnitDelay01; -- tPAES tpd_RCLK_PAENeg_sync : VitalDelayType01 := UnitDelay01; -- tPAEA tpd_RCLK_PAENeg_async : VitalDelayType01 := UnitDelay01; -- tERCLK tpd_RCLK_ERCLK : VitalDelayType01 := UnitDelay01; -- tCLKEN tpd_RCLK_ERENNeg : VitalDelayType01 := UnitDelay01; -- tpw values: pulse widths -- tRS tpw_MRSNeg_negedge : VitalDelayType := UnitDelay; -- tCLKL1 tpw_RCLK_SDR_negedge : VitalDelayType := UnitDelay; -- tCLKH1 tpw_RCLK_SDR_posedge : VitalDelayType := UnitDelay; -- tCLKL2 tpw_RCLK_DDR_negedge : VitalDelayType := UnitDelay; -- tCLKH2 tpw_RCLK_DDR_posedge : VitalDelayType := UnitDelay; -- tSCKL tpw_SCLK_negedge : VitalDelayType := UnitDelay; -- tSCKH tpw_SCLK_posedge : VitalDelayType := UnitDelay; --tPDL tpw_PDNeg_negedge : VitalDelayType := UnitDelay; -- tCLK1 tperiod_RCLK_SDR_posedge : VitalDelayType := UnitDelay; -- tCLK2 tperiod_RCLK_DDR_posedge : VitalDelayType := UnitDelay; -- tSCLK tperiod_SCLK_posedge : VitalDelayType := UnitDelay; -- tsetup values: setup times -- tDS tsetup_D0_WCLK : VitalDelayType := UnitDelay; -- tENS tsetup_RENNeg_RCLK : VitalDelayType := UnitDelay; -- tSDS tsetup_SI_SCLK : VitalDelayType := UnitDelay; -- tSENS tsetup_SWENNeg_SCLK : VitalDelayType := UnitDelay; -- tRSS tsetup_RENNeg_MRSNeg : VitalDelayType := UnitDelay; -- thold values: hold times -- tDH thold_D0_WCLK : VitalDelayType := UnitDelay; -- tENH thold_RENNeg_RCLK : VitalDelayType := UnitDelay; -- tSDH thold_SI_SCLK : VitalDelayType := UnitDelay; -- tSENH thold_SWENNeg_SCLK : VitalDelayType := UnitDelay; --tPDH thold_RENNeg_PDNeg : VitalDelayType := UnitDelay; -- trecovery values: release times -- tRSR trecovery_RENNeg_MRSNeg : VitalDelayType := UnitDelay; -- tSKEW1 (skew time /RCLK/WCLK(for EF/FF) tdevice_SKEW1 : VitalDelayType := UnitDelay; -- tSKEW2 (skew time /RCLK/WCLK(for EF/FF - DDR mode)) tdevice_SKEW2 : VitalDelayType := UnitDelay; -- tSKEW2 (skew time /RCLK/WCLK(for PAE/PAF) tdevice_SKEW3 : VitalDelayType := UnitDelay; -- number of FIFO instance FIFOnumber : NATURAL := 1; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( D0 : IN std_ulogic := 'U'; D1 : IN std_ulogic := 'U'; D2 : IN std_ulogic := 'U'; D3 : IN std_ulogic := 'U'; D4 : IN std_ulogic := 'U'; D5 : IN std_ulogic := 'U'; D6 : IN std_ulogic := 'U'; D7 : IN std_ulogic := 'U'; D8 : IN std_ulogic := 'U'; D9 : IN std_ulogic := 'U'; D10 : IN std_ulogic := 'U'; D11 : IN std_ulogic := 'U'; D12 : IN std_ulogic := 'U'; D13 : IN std_ulogic := 'U'; D14 : IN std_ulogic := 'U'; D15 : IN std_ulogic := 'U'; D16 : IN std_ulogic := 'U'; D17 : IN std_ulogic := 'U'; D18 : IN std_ulogic := 'U'; D19 : IN std_ulogic := 'Z'; Q0 : OUT std_logic := 'U'; Q1 : OUT std_logic := 'U'; Q2 : OUT std_logic := 'U'; Q3 : OUT std_logic := 'U'; Q4 : OUT std_logic := 'U'; Q5 : OUT std_logic := 'U'; Q6 : OUT std_logic := 'U'; Q7 : OUT std_logic := 'U'; Q8 : OUT std_logic := 'U'; Q9 : OUT std_logic := 'U'; Q10 : OUT std_logic := 'U'; Q11 : OUT std_logic := 'U'; Q12 : OUT std_logic := 'U'; Q13 : OUT std_logic := 'U'; Q14 : OUT std_logic := 'U'; Q15 : OUT std_logic := 'U'; Q16 : OUT std_logic := 'U'; Q17 : OUT std_logic := 'U'; Q18 : OUT std_logic := 'U'; Q19 : OUT std_logic := 'U'; MD : IN std_ulogic := 'U'; EFNeg : OUT std_ulogic := 'U'; ERCLK : OUT std_ulogic := 'U'; ERENNeg : OUT std_ulogic := 'U'; FFNeg : OUT std_ulogic := 'U'; FSEL0 : IN std_ulogic := 'U'; FSEL1 : IN std_ulogic := 'U'; FWFT : IN std_ulogic := 'U'; IOSEL : IN std_ulogic := 'U'; IW : IN std_ulogic := 'U'; PDNeg : IN std_ulogic := 'U'; MRSNeg : IN std_ulogic := 'U'; OENeg : IN std_ulogic := 'U'; OW : IN std_ulogic := 'U'; PAENeg : OUT std_ulogic := 'U'; PAFNeg : OUT std_ulogic := 'U'; PRSNeg : IN std_ulogic := 'U'; RCLK : IN std_ulogic := 'U'; RCSNeg : IN std_ulogic := 'U'; RENNeg : IN std_ulogic := 'U'; RDDR : IN std_ulogic := 'U'; PFM : IN std_ulogic := 'U'; SCLK : IN std_ulogic := 'U'; SWENNeg : IN std_ulogic := 'U'; SRENNeg : IN std_ulogic := 'U'; SI : IN std_ulogic := 'U'; SDO : OUT std_ulogic := 'U'; WCLK : IN std_ulogic := 'U'; WCSNeg : IN std_ulogic := 'U'; WENNeg : IN std_ulogic := 'U'; WDDR : IN std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of idt72t54242_onefifo : ENTITY IS TRUE; END idt72t54242_onefifo; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of idt72t54242_onefifo IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT partID : String := "IDT72T54242"; CONSTANT TotalLoc : POSITIVE := 32768; CONSTANT MaxData : POSITIVE := 1023; CONSTANT HiDbit : NATURAL := 19; SIGNAL D0_ipd : std_ulogic := 'U'; SIGNAL D1_ipd : std_ulogic := 'U'; SIGNAL D2_ipd : std_ulogic := 'U'; SIGNAL D3_ipd : std_ulogic := 'U'; SIGNAL D4_ipd : std_ulogic := 'U'; SIGNAL D5_ipd : std_ulogic := 'U'; SIGNAL D6_ipd : std_ulogic := 'U'; SIGNAL D7_ipd : std_ulogic := 'U'; SIGNAL D8_ipd : std_ulogic := 'U'; SIGNAL D9_ipd : std_ulogic := 'U'; SIGNAL D10_ipd : std_ulogic := 'U'; SIGNAL D11_ipd : std_ulogic := 'U'; SIGNAL D12_ipd : std_ulogic := 'U'; SIGNAL D13_ipd : std_ulogic := 'U'; SIGNAL D14_ipd : std_ulogic := 'U'; SIGNAL D15_ipd : std_ulogic := 'U'; SIGNAL D16_ipd : std_ulogic := 'U'; SIGNAL D17_ipd : std_ulogic := 'U'; SIGNAL D18_ipd : std_ulogic := 'U'; SIGNAL D19_ipd : std_ulogic := 'U'; SIGNAL MD_ipd : std_ulogic := 'U'; SIGNAL FSEL0_ipd : std_ulogic := 'U'; SIGNAL FSEL1_ipd : std_ulogic := 'U'; SIGNAL FWFT_ipd : std_ulogic := 'U'; SIGNAL IOSEL_ipd : std_ulogic := 'U'; SIGNAL IW_ipd : std_ulogic := 'U'; SIGNAL PDNeg_ipd : std_ulogic := 'U'; SIGNAL MRSNeg_ipd : std_ulogic := 'U'; SIGNAL OENeg_ipd : std_ulogic := 'U'; SIGNAL OW_ipd : std_ulogic := 'U'; SIGNAL PRSNeg_ipd : std_ulogic := 'U'; SIGNAL RCLK_ipd : std_ulogic := 'U'; SIGNAL RCSNeg_ipd : std_ulogic := 'U'; SIGNAL RENNeg_ipd : std_ulogic := 'U'; SIGNAL RDDR_ipd : std_ulogic := 'U'; SIGNAL PFM_ipd : std_ulogic := 'U'; SIGNAL SCLK_ipd : std_ulogic := 'U'; SIGNAL SWENNeg_ipd : std_ulogic := 'U'; SIGNAL SRENNeg_ipd : std_ulogic := 'U'; SIGNAL SI_ipd : std_ulogic := 'U'; SIGNAL WCLK_ipd : std_ulogic := 'U'; SIGNAL WCSNeg_ipd : std_ulogic := 'U'; SIGNAL WENNeg_ipd : std_ulogic := 'U'; SIGNAL WDDR_ipd : std_ulogic := 'U'; -- SKEW stuff ALIAS tSKEW1 : VitalDelayType IS tdevice_SKEW1; ALIAS tSKEW2 : VitalDelayType IS tdevice_SKEW2; ALIAS tSKEW3 : VitalDelayType IS tdevice_SKEW3; SIGNAL OpenIn, OpenOut : std_logic; SHARED VARIABLE FROMOE : BOOLEAN := false; SHARED VARIABLE FROMRCLK : BOOLEAN := false; SIGNAL FROMPD : std_ulogic := '0'; BEGIN -------------------------------------------------------------------------------- -- Dummy instances for exporting tSKEW vals from SDF file -- using DEVICE construct -------------------------------------------------------------------------------- SKEW1: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW1, tdevice_SKEW1)); SKEW2: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW2, tdevice_SKEW2)); SKEW3: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW3, tdevice_SKEW3)); ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay (D0_ipd, D0, tipd_D0); w_2 : VitalWireDelay (D1_ipd, D1, tipd_D1); w_3 : VitalWireDelay (D2_ipd, D2, tipd_D2); w_4 : VitalWireDelay (D3_ipd, D3, tipd_D3); w_5 : VitalWireDelay (D4_ipd, D4, tipd_D4); w_6 : VitalWireDelay (D5_ipd, D5, tipd_D5); w_7 : VitalWireDelay (D6_ipd, D6, tipd_D6); w_8 : VitalWireDelay (D7_ipd, D7, tipd_D7); w_9 : VitalWireDelay (D8_ipd, D8, tipd_D8); w_10 : VitalWireDelay (D9_ipd, D9, tipd_D9); w_11 : VitalWireDelay (D10_ipd, D10, tipd_D10); w_12 : VitalWireDelay (D11_ipd, D11, tipd_D11); w_13 : VitalWireDelay (D12_ipd, D12, tipd_D12); w_14 : VitalWireDelay (D13_ipd, D13, tipd_D13); w_15 : VitalWireDelay (D14_ipd, D14, tipd_D14); w_16 : VitalWireDelay (D15_ipd, D15, tipd_D15); w_17 : VitalWireDelay (D16_ipd, D16, tipd_D16); w_18 : VitalWireDelay (D17_ipd, D17, tipd_D17); w_19 : VitalWireDelay (D18_ipd, D18, tipd_D18); w_20 : VitalWireDelay (D19_ipd, D19, tipd_D19); w_21 : VitalWireDelay (MD_ipd, MD, tipd_MD); w_22 : VitalWireDelay (FSEL0_ipd, FSEL0, tipd_FSEL0); w_23 : VitalWireDelay (FSEL1_ipd, FSEL1, tipd_FSEL1); w_24 : VitalWireDelay (FWFT_ipd, FWFT, tipd_FWFT); w_25 : VitalWireDelay (IOSEL_ipd, IOSEL, tipd_IOSEL); w_26 : VitalWireDelay (IW_ipd, IW, tipd_IW); w_27 : VitalWireDelay (PDNeg_ipd, PDNeg, tipd_PDNeg); w_28 : VitalWireDelay (MRSNeg_ipd, MRSNeg, tipd_MRSNeg); w_29 : VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg); w_30 : VitalWireDelay (OW_ipd, OW, tipd_OW); w_31 : VitalWireDelay (PRSNeg_ipd, PRSNeg, tipd_PRSNeg); w_32 : VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK); w_33 : VitalWireDelay (RCSNeg_ipd, RCSNeg, tipd_RCSNeg); w_34 : VitalWireDelay (RENNeg_ipd, RENNeg, tipd_RENNeg); w_35 : VitalWireDelay (RDDR_ipd, RDDR, tipd_RDDR); w_36 : VitalWireDelay (PFM_ipd, PFM, tipd_PFM); w_37 : VitalWireDelay (SCLK_ipd, SCLK, tipd_SCLK); w_38 : VitalWireDelay (SWENNeg_ipd, SWENNeg, tipd_SWENNeg); w_39 : VitalWireDelay (SRENNeg_ipd, SRENNeg, tipd_SRENNeg); w_40 : VitalWireDelay (SI_ipd, SI, tipd_SI); w_41 : VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK); w_42 : VitalWireDelay (WCSNeg_ipd, WCSNeg, tipd_WCSNeg); w_43 : VitalWireDelay (WENNeg_ipd, WENNeg, tipd_WENNeg); w_44 : VitalWireDelay (WDDR_ipd, WDDR, tipd_WDDR); END BLOCK; ---------------------------------------------------------------------------- -- Main Behavior Block ---------------------------------------------------------------------------- Behavior: BLOCK PORT ( DIn : IN std_logic_vector(19 DOWNTO 0); MDIn : IN std_ulogic := 'U'; FSEL0In : IN std_ulogic := 'U'; FSEL1In : IN std_ulogic := 'U'; FWFTIn : IN std_ulogic := 'U'; IOSELIn : IN std_ulogic := 'U'; IWIn : IN std_ulogic := 'U'; PDNegIn : IN std_ulogic := 'U'; MRSNegIn : IN std_ulogic := 'U'; OENegIn : IN std_ulogic := 'U'; OWIn : IN std_ulogic := 'U'; PRSNegIn : IN std_ulogic := 'U'; RCLKIn : IN std_ulogic := 'U'; RCSNegIn : IN std_ulogic := 'U'; RENNegIn : IN std_ulogic := 'U'; RDDRIn : IN std_ulogic := 'U'; PFMIn : IN std_ulogic := 'U'; SCLKIn : IN std_ulogic := 'U'; SWENNegIn : IN std_ulogic := 'U'; SRENNegIn : IN std_ulogic := 'U'; SIIn : IN std_ulogic := 'U'; WCLKIn : IN std_ulogic := 'U'; WCSNegIn : IN std_ulogic := 'U'; WENNegIn : IN std_ulogic := 'U'; WDDRIn : IN std_ulogic := 'U'; QOut : OUT std_logic_vector(19 downto 0); EFNegOut : OUT std_ulogic := 'U'; ERCLKOut : OUT std_ulogic := 'U'; ERENNegOut : OUT std_ulogic := 'U'; FFNegOut : OUT std_ulogic := 'U'; PAENegOut : OUT std_ulogic := 'U'; PAFNegOut : OUT std_ulogic := 'U'; SDOOut : OUT std_ulogic := 'U' ); PORT MAP ( DIn(0) => D0_ipd, DIn(1) => D1_ipd, DIn(2) => D2_ipd, DIn(3) => D3_ipd, DIn(4) => D4_ipd, DIn(5) => D5_ipd, DIn(6) => D6_ipd, DIn(7) => D7_ipd, DIn(8) => D8_ipd, DIn(9) => D9_ipd, DIn(10) => D10_ipd, DIn(11) => D11_ipd, DIn(12) => D12_ipd, DIn(13) => D13_ipd, DIn(14) => D14_ipd, DIn(15) => D15_ipd, DIn(16) => D16_ipd, DIn(17) => D17_ipd, DIn(18) => D18_ipd, DIn(19) => D19_ipd, QOut(0) => Q0, QOut(1) => Q1, QOut(2) => Q2, QOut(3) => Q3, QOut(4) => Q4, QOut(5) => Q5, QOut(6) => Q6, QOut(7) => Q7, QOut(8) => Q8, QOut(9) => Q9, QOut(10) => Q10, QOut(11) => Q11, QOut(12) => Q12, QOut(13) => Q13, QOut(14) => Q14, QOut(15) => Q15, QOut(16) => Q16, QOut(17) => Q17, QOut(18) => Q18, QOut(19) => Q19, MDIn => To_UX01(MD_ipd), FSEL0In => To_UX01(FSEL0_ipd), FSEL1In => To_UX01(FSEL1_ipd), FWFTIn => To_UX01(FWFT_ipd), IOSELIn => To_UX01(IOSEL_ipd), IWIn => To_UX01(IW_ipd), PDNegIn => To_UX01(PDNeg_ipd), MRSNegIn => To_UX01(MRSNeg_ipd), OENegIn => To_UX01(OENeg_ipd), OWIn => To_UX01(OW_ipd), PRSNegIn => To_UX01(PRSNeg_ipd), RCLKIn => RCLK_ipd, RCSNegIn => To_UX01(RCSNeg_ipd), RENNegIn => To_UX01(RENNeg_ipd), RDDRIn => To_UX01(RDDR_ipd), PFMIn => To_UX01(PFM_ipd), SCLKIn => SCLK_ipd, SWENNegIn => SWENNeg_ipd, SRENNegIn => SRENNeg_ipd, SIIn => SI_ipd, WCLKIn => WCLK_ipd, WCSNegIn => To_UX01(WCSNeg_ipd), WENNegIn => To_UX01(WENNeg_ipd), WDDRIn => To_UX01(WDDR_ipd), EFNegOut => EFNeg, ERCLKOut => ERCLK, ERENNegOut => ERENNeg, FFNegOut => FFNeg, PAENegOut => PAENeg, PAFNegOut => PAFNeg, SDOOut => SDO ); SIGNAL Q_zd : std_logic_vector(19 downto 0) := (others => 'Z'); SIGNAL mreset : boolean := false; SIGNAL time_flag_for_OE : std_logic := '0'; TYPE mode_type IS (SDR, DDR); TYPE match_type IS (DDR20, DDR10, SDR20, SDR10); TYPE offset_type IS ARRAY (0 TO 3) OF positive; TYPE last_done_type is (write, read, none); TYPE memory_model_type is (normal, mapped); TYPE device_mode_type is (QUAD, DUAL); TYPE PFM_mode_type is (async,sync); BEGIN ------------------------------------------------------------------------ -- Behavior Process ------------------------------------------------------------------------ Fifo : PROCESS (DIn, MDIn, WCLKIn, MRSNegIn, PRSNegIn, FWFTIn, OWIn, FSEL0In, FSEL1In, WENNegIn, IWIn, OENegIn, RENNegIn, SWENNegIn, RCLKIn, PDNegIn, RCSNegIn, RDDRIn, SCLKIn, SRENNegIn, SIIn, WCSNegIn, WDDRIn) CONSTANT offsetps : offset_type := (7, 127, 63, 255); -- Timing Check Variables VARIABLE Tviol_D_WCLK : X01 := '0'; VARIABLE TD_D_WCLK : VitalTimingDataType; VARIABLE Tviol_D_WCLK_DDR : X01 := '0'; VARIABLE TD_D_WCLK_DDR : VitalTimingDataType; VARIABLE Tviol_RENNeg_RCLK : X01 := '0'; VARIABLE TD_RENNeg_RCLK : VitalTimingDataType; VARIABLE Tviol_WENNeg_WCLK : X01 := '0'; VARIABLE TD_WENNeg_WCLK : VitalTimingDataType; VARIABLE Tviol_RCSNeg_RCLK : X01 := '0'; VARIABLE TD_RCSNeg_RCLK : VitalTimingDataType; VARIABLE Tviol_SI_SCLK : X01 := '0'; VARIABLE TD_SI_SCLK : VitalTimingDataType; VARIABLE Tviol_SWENNeg_SCLK : X01 := '0'; VARIABLE TD_SWENNeg_SCLK : VitalTimingDataType; VARIABLE Tviol_SRENNeg_SCLK : X01 := '0'; VARIABLE TD_SRENNeg_SCLK : VitalTimingDataType; VARIABLE Tviol_RENNeg_PDNeg : X01 := '0'; VARIABLE TD_RENNeg_PDNeg : VitalTimingDataType; VARIABLE Tviol_WENNeg_PDNeg : X01 := '0'; VARIABLE TD_WENNeg_PDNeg : VitalTimingDataType; VARIABLE Tviol_RENNeg_MRSNeg : X01 := '0'; VARIABLE TD_RENNeg_MRSNeg : VitalTimingDataType; VARIABLE Tviol_WENNeg_MRSNeg : X01 := '0'; VARIABLE TD_WENNeg_MRSNeg : VitalTimingDataType; VARIABLE Tviol_SWENNeg_MRSNeg : X01 := '0'; VARIABLE TD_SWENNeg_MRSNeg : VitalTimingDataType; VARIABLE Tviol_SRENNeg_MRSNeg : X01 := '0'; VARIABLE TD_SRENNeg_MRSNeg : VitalTimingDataType; VARIABLE Tviol_FWFT_MRSNeg : X01 := '0'; VARIABLE TD_FWFT_MRSNeg : VitalTimingDataType; VARIABLE Tviol_FSEL1_MRSNeg : X01 := '0'; VARIABLE TD_FSEL1_MRSNeg : VitalTimingDataType; VARIABLE Tviol_FSEL0_MRSNeg : X01 := '0'; VARIABLE TD_FSEL0_MRSNeg : VitalTimingDataType; VARIABLE Tviol_MD_MRSNeg : X01 := '0'; VARIABLE TD_MD_MRSNeg : VitalTimingDataType; VARIABLE Tviol_OW_MRSNeg : X01 := '0'; VARIABLE TD_OW_MRSNeg : VitalTimingDataType; VARIABLE Tviol_IW_MRSNeg : X01 := '0'; VARIABLE TD_IW_MRSNeg : VitalTimingDataType; VARIABLE Tviol_WDDR_MRSNeg : X01 := '0'; VARIABLE TD_WDDR_MRSNeg : VitalTimingDataType; VARIABLE Tviol_RDDR_MRSNeg : X01 := '0'; VARIABLE TD_RDDR_MRSNeg : VitalTimingDataType; VARIABLE Tviol_PFM_MRSNeg : X01 := '0'; VARIABLE TD_PFM_MRSNeg : VitalTimingDataType; VARIABLE Tviol_IOSEL_MRSNeg : X01 := '0'; VARIABLE TD_IOSEL_MRSNeg : VitalTimingDataType; VARIABLE Tviol_RENNeg_PRSNeg : X01 := '0'; VARIABLE TD_RENNeg_PRSNeg : VitalTimingDataType; VARIABLE Tviol_WENNeg_PRSNeg : X01 := '0'; VARIABLE TD_WENNeg_PRSNeg : VitalTimingDataType; VARIABLE Tviol_SWENNeg_PRSNeg: X01 := '0'; VARIABLE TD_SWENNeg_PRSNeg : VitalTimingDataType; VARIABLE Tviol_SRENNeg_PRSNeg: X01 := '0'; VARIABLE TD_SRENNeg_PRSNeg : VitalTimingDataType; VARIABLE Rviol_RENNeg_MRSNeg : X01 := '0'; VARIABLE RD_RENNeg_MRSNeg : VitalTimingDataType; VARIABLE Rviol_WENNeg_MRSNeg : X01 := '0'; VARIABLE RD_WENNeg_MRSNeg : VitalTimingDataType; VARIABLE Rviol_RENNeg_PRSNeg : X01 := '0'; VARIABLE RD_RENNeg_PRSNeg : VitalTimingDataType; VARIABLE Rviol_WENNeg_PRSNeg : X01 := '0'; VARIABLE RD_WENNeg_PRSNeg : VitalTimingDataType; VARIABLE Pviol_MRSNeg : X01 := '0'; VARIABLE PD_MRSNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRSNeg : X01 := '0'; VARIABLE PD_PRSNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RCLK1 : X01 := '0'; VARIABLE PD_RCLK1 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RCLK2 : X01 := '0'; VARIABLE PD_RCLK2 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WCLK1 : X01 := '0'; VARIABLE PD_WCLK1 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WCLK2 : X01 := '0'; VARIABLE PD_WCLK2 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_SCLK : X01 := '0'; VARIABLE PD_SCLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PDNeg : X01 := '0'; VARIABLE PD_PDNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE mode_wr : mode_type := SDR; VARIABLE mode_rd : mode_type := SDR; VARIABLE in_mode : match_type := SDR10; VARIABLE out_mode : match_type := SDR10; VARIABLE wrote_in : boolean := false; VARIABLE read_out : boolean := false; VARIABLE device_mode : device_mode_type := QUAD; VARIABLE PFM_mode : PFM_mode_type := sync; -- Memory array declaration TYPE MemStore IS ARRAY (0 to TotalLOC + 1) OF INTEGER RANGE -2 TO MaxData; -- uninitialized memory -2 -- unknown or corrupted memory -1 -- Functionality Results Variables VARIABLE Violation : X01 := '0'; VARIABLE EFNeg_zd : std_ulogic; VARIABLE FFNeg_zd : std_ulogic; VARIABLE PAFNeg_dly : std_ulogic; VARIABLE PAFNeg_zd : std_ulogic; VARIABLE PAENeg_dly : std_ulogic; VARIABLE PAENeg_zd : std_ulogic; VARIABLE ERCLK_zd : std_ulogic; VARIABLE ERENNeg_zd : std_ulogic; VARIABLE Qreg : std_logic_vector(19 downto 0) := (others => '0'); VARIABLE Qreg_tmp: std_logic_vector(39 downto 0):=(others => '0'); VARIABLE SDO_zd : std_ulogic; VARIABLE fwft : boolean := false; VARIABLE iw : boolean := false; VARIABLE ow : boolean := false; VARIABLE memA : MemStore; VARIABLE memB : MemStore; VARIABLE Data1 : Integer := 0; VARIABLE Data2 : Integer := 0; VARIABLE memory_model : memory_model_type := normal; VARIABLE rdptr : natural RANGE 0 TO TotalLOC + 1 := 0; --read pointer VARIABLE wrptr : natural RANGE 0 TO TotalLOC + 1 := 0;--write pointer VARIABLE rdptr_next : natural RANGE 0 TO TotalLOC + 1 := 0; --read pointer VARIABLE wrptr_next : natural RANGE 0 TO TotalLOC + 1 := 0;--write pointer VARIABLE paeoff : natural RANGE 0 TO TotalLOC; --pae offset VARIABLE pafoff : natural RANGE 0 TO TotalLOC; --paf offset VARIABLE opi : natural RANGE 0 TO 7; --offset preset index VARIABLE count : natural RANGE 0 TO TotalLOC + 1; --memory used VARIABLE fwftcnt : natural RANGE 0 TO 3; -- fwft RCLK counter VARIABLE fwftcnt1 : natural RANGE 0 TO 3; -- fwft output VARIABLE fwftvar : boolean := false; -- fwft flag for outreg VARIABLE do_fw : boolean := false; VARIABLE fw_done : boolean := false; VARIABLE fwcnt : natural := 0; VARIABLE opireg : std_logic_vector(1 downto 0); VARIABLE outreg : std_logic_vector(39 downto 0); VARIABLE outtmp : std_logic_vector(39 downto 0); VARIABLE rd_upd_flg : boolean := false; VARIABLE wr_upd_flg : boolean := false; VARIABLE write_clk_paf : Natural := 0; VARIABLE read_clk_pae : Natural := 0; VARIABLE delayed_pae : boolean := false; VARIABLE delayed_paf : boolean := false; VARIABLE Eflagcnt : natural := 0; VARIABLE PAEflagcnt : natural := 0; VARIABLE PAFflagcnt : natural := 0; VARIABLE Fflagcnt : natural := 0; VARIABLE TotalLoc1: natural := TotalLoc; VARIABLE count_rcycle : natural := 0; VARIABLE count_wcycle : natural := 0; VARIABLE tRCLKposedge : Time := 0 ns; VARIABLE tWCLKposedge : Time := 0 ns; VARIABLE tRCLKnegedge : Time := 0 ns; VARIABLE tWCLKnegedge : Time := 0 ns; VARIABLE tOEnegedge : Time := 0 ns; VARIABLE minskew1RW : boolean := true; VARIABLE minskew2RW : boolean := true; VARIABLE minskew3RW : boolean := true; VARIABLE minskew1WR : boolean := true; VARIABLE minskew2WR : boolean := true; VARIABLE minskew3WR : boolean := true; VARIABLE last_done : last_done_type := none; VARIABLE flag_FF : std_logic := '0'; VARIABLE flag_EF : std_logic := '0'; VARIABLE flag_PAF : std_logic := '0'; VARIABLE flag_PAE : std_logic := '0'; VARIABLE pass_EF, pass_FF, pass_PAE, pass_PAF : boolean := false; VARIABLE bm_Incnt : natural RANGE 0 TO 7 := 0; VARIABLE bm_Outcnt: natural RANGE 0 TO 7 := 0; VARIABLE fs_Incnt : natural RANGE 0 to 120 := 0; VARIABLE tmp_ser_in : std_logic_vector(119 downto 0) := (OTHERS=>'0'); -- Output Glitch Detection Variables VARIABLE FFNeg_GlitchData : VitalGlitchDataType; VARIABLE PAFNeg_GlitchData : VitalGlitchDataType; VARIABLE EFNeg_GlitchData : VitalGlitchDataType; VARIABLE PAENeg_GlitchData : VitalGlitchDataType; VARIABLE ERCLK_GlitchData : VitalGlitchDataType; VARIABLE ERENNeg_GlitchData : VitalGlitchDataType; VARIABLE SDO_GlitchData : VitalGlitchDataType; PROCEDURE master_reset IS BEGIN mreset <= false, true AFTER 200 ns; -- valid reset signal fwftcnt := 0; PAENeg_zd := '0'; PAFNeg_zd := '1'; PAENeg_dly := '0'; PAFNeg_dly := '1'; TotalLoc1 := TotalLoc; rdptr := 0; wrptr := 0; count := 0; fw_done := false; last_done := none; count_rcycle := 0; count_wcycle := 0; -- configuration section IF FWFTIn = '1' THEN fwft := true; -- fwft mode EFNeg_zd := '1'; FFNeg_zd := '0'; ELSE fwft := false; --idt standard mode EFNeg_zd := '0'; FFNeg_zd := '1'; END IF; IF MDIn = '0' THEN device_mode := DUAL; ELSE device_mode := QUAD; END IF; IF PFMIn = '1' THEN PFM_mode := sync; ELSE PFM_mode := async; END IF; --bus matching byte counter bm_Incnt :=0; bm_Outcnt:=0; IF WDDRIn = '0' THEN mode_wr := SDR; ELSIF WDDRIn = '1' THEN mode_wr := DDR; END IF; IF RDDRIn = '0' THEN mode_rd := SDR; ELSIF RDDRIn = '1' THEN mode_rd := DDR; END IF; opireg := (FSEL1In, FSEL0In); opi := To_Nat(opireg); paeoff := offsetps(opi); -- bus-match and rate mode - select input-output combination IF (device_mode = QUAD) OR (device_mode = DUAL AND IWIn = '0' AND OWIn = '0') THEN IF mode_wr = SDR THEN in_mode := SDR10; ELSE in_mode := DDR10; END IF; IF mode_rd = SDR THEN out_mode := SDR10; ELSE out_mode := DDR10; END IF; ELSIF device_mode = DUAL AND IWIn = '1' AND OWIn = '0' THEN IF mode_wr = SDR THEN in_mode := SDR20; ELSE in_mode := DDR20; END IF; IF mode_rd = SDR THEN out_mode := SDR10; ELSE out_mode := DDR10; END IF; ELSIF device_mode = DUAL AND IWIn = '0' AND OWIn = '1' THEN IF mode_wr = SDR THEN in_mode := SDR10; ELSE in_mode := DDR10; END IF; IF mode_rd = SDR THEN out_mode := SDR20; ELSE out_mode := DDR20; END IF; ELSIF device_mode = DUAL AND IWIn = '1' AND OWIn = '1' THEN IF mode_wr = SDR THEN in_mode := SDR20; ELSE in_mode := DDR20; END IF; IF mode_rd = SDR THEN out_mode := SDR20; ELSE out_mode := DDR20; END IF; END IF; IF in_mode=SDR10 AND out_mode=SDR10 THEN memory_model := normal; TotalLoc1 := TotalLoc; ELSIF (in_mode=DDR10 AND out_mode/=DDR20) OR (in_mode=SDR10 AND out_mode/=DDR20) OR (in_mode/=DDR20 AND out_mode=SDR10) OR (in_mode/=DDR20 AND out_mode=SDR20) OR (in_mode=SDR20 AND out_mode/=DDR20) THEN memory_model := mapped; TotalLoc1 := TotalLoc/2; paeoff := (paeoff - 1)/2; ELSE memory_model := mapped; TotalLoc1 := TotalLoc/4; paeoff := (paeoff - 1)/4; END IF; pafoff := TotalLoc1 - paeoff; outreg := (others => '0'); Qreg := (others => '0'); END master_reset; PROCEDURE partial_reset IS BEGIN mreset <= false, true AFTER 200 ns; -- valid reset signal fwftcnt := 0; PAENeg_zd := '0'; PAFNeg_zd := '1'; PAENeg_dly := '0'; PAFNeg_dly := '1'; rdptr := 0; wrptr := 0; count := 0; fw_done := false; last_done := none; count_rcycle := 0; count_wcycle := 0; IF fwft THEN EFNeg_zd := '1'; FFNeg_zd := '0'; ELSE EFNeg_zd := '0'; FFNeg_zd := '1'; END IF; Qreg := (others => '0'); bm_Incnt :=0; bm_Outcnt:=0; END partial_reset; PROCEDURE count_skew IS BEGIN IF (tWCLKposedge - tRCLKposedge) >= tSKEW1 THEN minskew1RW := true; ELSE minskew1RW := false; END IF; IF (tWCLKposedge - tRCLKnegedge) >= tSKEW2 THEN minskew2RW := true; ELSE minskew2RW := false; END IF; IF (tWCLKposedge - tRCLKposedge) >= tSKEW3 THEN minskew3RW := true; ELSE minskew3RW := false; END IF; IF (tRCLKposedge - tWCLKposedge) >= tSKEW1 THEN minskew1WR := true; ELSE minskew1WR := false; END IF; IF (tRCLKposedge - tWCLKnegedge) >= tSKEW2 THEN minskew2WR := true; ELSE minskew2WR := false; END IF; IF (tRCLKposedge - tWCLKposedge) >= tSKEW3 THEN minskew3WR := true; ELSE minskew3WR := false; END IF; END count_skew; PROCEDURE write_input IS BEGIN IF Violation = '0' THEN IF DIn(19 downto 10) /= "ZZZZZZZZZZ" AND device_mode = DUAL THEN Data2 := to_nat(DIn(19 downto 10)); END IF; IF DIn(9 downto 0) /= "ZZZZZZZZZZ" THEN Data1 := to_nat(DIn(9 downto 0)); END IF; ELSE Data2 := -1; Data1 := -1; END IF; END write_input; PROCEDURE generate_output(pointer : IN Natural) IS BEGIN IF (RCLKIn = '1') THEN time_flag_for_OE <= '1', '0' AFTER tpd_RCLK_Q0(trz0); FROMRCLK := true; FROMOE := false; END IF; IF memA(pointer) >= 0 THEN Qreg_tmp(19 downto 10) := to_slv(memA(pointer),10); ELSE Qreg_tmp(19 downto 10) := (OTHERS => 'X'); END IF; IF memB(pointer) >= 0 THEN Qreg_tmp(9 downto 0) := to_slv(memB(pointer),10); ELSE Qreg_tmp(9 downto 0) := (OTHERS => 'X'); END IF; END generate_output; PROCEDURE write_register IS BEGIN IF rising_edge(SCLKIn) THEN IF device_mode = QUAD THEN tmp_ser_in(118 downto 0) := tmp_ser_in(119 downto 1); tmp_ser_in(119) := SIIn; IF FIFOnumber = 0 THEN pafoff:= to_nat(tmp_ser_in(119 downto 105)); paeoff:= to_nat(tmp_ser_in(104 downto 90)); ELSIF FIFOnumber = 1 THEN pafoff:= to_nat(tmp_ser_in(89 downto 75)); paeoff:= to_nat(tmp_ser_in(74 downto 60)); ELSIF FIFOnumber = 2 THEN pafoff:= to_nat(tmp_ser_in(59 downto 45)); paeoff:= to_nat(tmp_ser_in(44 downto 30)); ELSE pafoff:= to_nat(tmp_ser_in(29 downto 15)); paeoff:= to_nat(tmp_ser_in(14 downto 0)); END IF; ELSIF device_mode = DUAL AND IWIn = '0' AND OWIn = '0' THEN tmp_ser_in(58 downto 0) := tmp_ser_in(59 downto 1); tmp_ser_in(59) := SIIn; IF FIFOnumber = 0 THEN pafoff:= to_nat(tmp_ser_in(59 downto 45)); paeoff:= to_nat(tmp_ser_in(44 downto 30)); ELSE pafoff:= to_nat(tmp_ser_in(29 downto 15)); paeoff:= to_nat(tmp_ser_in(14 downto 0)); END IF; ELSIF (device_mode = DUAL AND (IWIn = '1' OR OWIn = '1')) THEN tmp_ser_in(54 downto 0) := tmp_ser_in(55 downto 1); tmp_ser_in(55) := SIIn; IF FIFOnumber = 0 THEN pafoff:= to_nat(tmp_ser_in(55 downto 42)); paeoff:= to_nat(tmp_ser_in(41 downto 28)); ELSE pafoff:= to_nat(tmp_ser_in(27 downto 14)); paeoff:= to_nat(tmp_ser_in(13 downto 0)); END IF; END IF; IF mode_wr = DDR or mode_rd = DDR THEN IF memory_model = mapped THEN pafoff:=pafoff/2; paeoff:=paeoff/2; pafoff:=TotalLoc1-pafoff; END IF; ELSE IF memory_model = mapped THEN pafoff:=TotalLoc1-pafoff; ELSE pafoff:=TotalLoc-pafoff; END IF; END IF; END IF; END write_register; PROCEDURE read_register IS BEGIN IF rising_edge(SCLKIn) THEN IF device_mode = QUAD THEN IF fs_Incnt < 120 THEN SDO_zd := tmp_ser_in(fs_Incnt); fs_Incnt:=fs_Incnt+1; END IF; IF fs_Incnt >= 119 THEN fs_Incnt:=0; END IF; ELSIF device_mode = DUAL AND IWIn = '0' AND OWIn = '0' THEN IF fs_Incnt < 60 THEN SDO_zd := tmp_ser_in(fs_Incnt); fs_Incnt:=fs_Incnt+1; END IF; IF fs_Incnt >= 59 THEN fs_Incnt:=0; END IF; ELSE IF fs_Incnt < 56 THEN SDO_zd := tmp_ser_in(fs_Incnt); fs_Incnt:=fs_Incnt+1; END IF; IF fs_Incnt >= 55 THEN fs_Incnt:=0; END IF; END IF; END IF; END read_register; BEGIN IF ((FIFOnumber = 0 OR FIFOnumber = 2) AND MDIn = '0') OR MDIn = '1' THEN ---------------------------------------------------------------------------- -- Timing Check Section ---------------------------------------------------------------------------- IF (TimingChecksOn) THEN -- tDS, tDH VitalSetupHoldCheck ( TestSignal => DIn, TestSignalName => "D", RefSignal => WCLKIn, RefSignalName => "WCLK", SetupHigh => tsetup_D0_WCLK, SetupLow => tsetup_D0_WCLK, HoldHigh => thold_D0_WCLK, HoldLow => thold_D0_WCLK, CheckEnabled => (WENNegIn='0' AND WCSNegIn='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_D_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D_WCLK ); VitalSetupHoldCheck ( TestSignal => DIn, TestSignalName => "D", RefSignal => WCLKIn, RefSignalName => "WCLK", SetupHigh => tsetup_D0_WCLK, SetupLow => tsetup_D0_WCLK, HoldHigh => thold_D0_WCLK, HoldLow => thold_D0_WCLK, CheckEnabled => (WENNegIn='0' AND WCSNegIn='0' AND mode_wr=DDR), RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_D_WCLK_DDR, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D_WCLK_DDR ); -- tENS, tENH VitalSetupHoldCheck ( TestSignal => RENNegIn, TestSignalName => "RENNeg", RefSignal => RCLKIn, RefSignalName => "RCLK", SetupHigh => tsetup_RENNeg_RCLK, SetupLow => tsetup_RENNeg_RCLK, HoldHigh => thold_RENNeg_RCLK, HoldLow => thold_RENNeg_RCLK, CheckEnabled => (RCSNegIn='0' AND RENNegIn='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RENNeg_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RENNeg_RCLK ); VitalSetupHoldCheck ( TestSignal => WENNegIn, TestSignalName => "WENNeg", RefSignal => WCLKIn, RefSignalName => "WCLK", SetupHigh => tsetup_RENNeg_RCLK, SetupLow => tsetup_RENNeg_RCLK, HoldHigh => thold_RENNeg_RCLK, HoldLow => thold_RENNeg_RCLK, CheckEnabled => (WCSNegIn='0' AND WENNegIn='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_WENNeg_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_WCLK ); VitalSetupHoldCheck ( TestSignal => RCSNegIn, TestSignalName => "RCSNeg", RefSignal => RCLKIn, RefSignalName => "RCLK", SetupHigh => tsetup_RENNeg_RCLK, SetupLow => tsetup_RENNeg_RCLK, HoldHigh => thold_RENNeg_RCLK, HoldLow => thold_RENNeg_RCLK, CheckEnabled => (RCSNegIn='0' AND RENNegIn='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RCSNeg_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RCSNeg_RCLK ); -- tSDS, tSDH VitalSetupHoldCheck ( TestSignal => SIIn, TestSignalName => "SI", RefSignal => SCLKIn, RefSignalName => "SCLK", SetupHigh => tsetup_SI_SCLK, SetupLow => tsetup_SI_SCLK, HoldHigh => thold_SI_SCLK, HoldLow => thold_SI_SCLK, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_SI_SCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SI_SCLK ); -- tSENS, tSENH VitalSetupHoldCheck ( TestSignal => SWENNegIn, TestSignalName => "SWENNeg", RefSignal => SCLKIn, RefSignalName => "SCLK", SetupHigh => tsetup_SWENNeg_SCLK, SetupLow => tsetup_SWENNeg_SCLK, HoldHigh => thold_SWENNeg_SCLK, HoldLow => thold_SWENNeg_SCLK, CheckEnabled => (SWENNeg = '0'), ---????? RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_SWENNeg_SCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SWENNeg_SCLK ); VitalSetupHoldCheck ( TestSignal => SRENNegIn, TestSignalName => "SRENNeg", RefSignal => SCLKIn, RefSignalName => "SCLK", SetupHigh => tsetup_SWENNeg_SCLK, SetupLow => tsetup_SWENNeg_SCLK, HoldHigh => thold_SWENNeg_SCLK, HoldLow => thold_SWENNeg_SCLK, CheckEnabled => (SRENNeg = '0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_SRENNeg_SCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SRENNeg_SCLK ); VitalSetupHoldCheck ( TestSignal => RENNegIn, TestSignalName => "RENNeg", RefSignal => PDNegIn, RefSignalName => "PDNeg", HoldHigh => thold_RENNeg_PDNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RENNeg_PDNEg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RENNeg_PDNeg ); VitalSetupHoldCheck ( TestSignal => WENNegIn, TestSignalName => "WENNeg", RefSignal => PDNegIn, RefSignalName => "PDNeg", HoldHigh => thold_RENNeg_PDNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_WENNeg_PDNEg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_PDNeg ); -- tRSS VitalSetupHoldCheck ( TestSignal => RENNegIn, TestSignalName => "RENNeg", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_RENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RENNeg_MRSNeg ); VitalSetupHoldCheck ( TestSignal => WENNegIn, TestSignalName => "WENNeg", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_WENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_MRSNeg ); VitalSetupHoldCheck ( TestSignal => SWENNegIn, TestSignalName => "SWENNeg", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_SWENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SWENNeg_MRSNeg ); VitalSetupHoldCheck ( TestSignal => SRENNegIn, TestSignalName => "SRENNeg", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_SRENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SRENNeg_MRSNeg ); VitalSetupHoldCheck ( TestSignal => FWFTIn, TestSignalName => "FWFT", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_FWFT_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FWFT_MRSNeg ); VitalSetupHoldCheck ( TestSignal => FSEL1In, TestSignalName => "FSEL1", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_FSEL1_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FSEL1_MRSNeg ); VitalSetupHoldCheck ( TestSignal => FSEL0In, TestSignalName => "FSEL0", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_FSEL0_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FSEL0_MRSNeg ); VitalSetupHoldCheck ( TestSignal => MDIn, TestSignalName => "MD", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_MD_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_MD_MRSNeg ); VitalSetupHoldCheck ( TestSignal => OWIn, TestSignalName => "OW", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_OW_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_OW_MRSNeg ); VitalSetupHoldCheck ( TestSignal => IWIn, TestSignalName => "IW", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_IW_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IW_MRSNeg ); VitalSetupHoldCheck ( TestSignal => WDDRIn, TestSignalName => "WDDR", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_WDDR_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WDDR_MRSNeg ); VitalSetupHoldCheck ( TestSignal => RDDRIn, TestSignalName => "RDDR", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_RDDR_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RDDR_MRSNeg ); VitalSetupHoldCheck ( TestSignal => PFMIn, TestSignalName => "PFM", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_PFM_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_PFM_MRSNeg ); VitalSetupHoldCheck ( TestSignal => IOSELIn, TestSignalName => "IOSEL", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_IOSEL_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IOSEL_MRSNeg ); -- tRSS VitalSetupHoldCheck ( TestSignal => RENNegIn, TestSignalName => "RENNeg", RefSignal => PRSNegIn, RefSignalName => "PRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_RENNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RENNeg_PRSNeg ); VitalSetupHoldCheck ( TestSignal => WENNegIn, TestSignalName => "WENNeg", RefSignal => PRSNegIn, RefSignalName => "PRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_WENNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_PRSNeg ); VitalSetupHoldCheck ( TestSignal => SWENNegIn, TestSignalName => "SWENNeg", RefSignal => PRSNegIn, RefSignalName => "PRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_SWENNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SWENNeg_PRSNeg ); VitalSetupHoldCheck ( TestSignal => SRENNegIn, TestSignalName => "SRENNeg", RefSignal => PRSNegIn, RefSignalName => "PRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_SRENNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SRENNeg_PRSNeg ); -- tRSR VitalRecoveryRemovalCheck ( TestSignal => RENNegIn, TestSignalName => "RENNeg", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", Recovery => trecovery_RENNeg_MRSNeg, ActiveLow => true, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => RD_RENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_RENNeg_MRSNeg ); VitalRecoveryRemovalCheck ( TestSignal => WENNegIn, TestSignalName => "WENNeg", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", Recovery => trecovery_RENNeg_MRSNeg, ActiveLow => true, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => RD_WENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_WENNeg_MRSNeg ); VitalRecoveryRemovalCheck ( TestSignal => RENNegIn, TestSignalName => "RENNeg", RefSignal => PRSNegIn, RefSignalName => "PRSNeg", Recovery => trecovery_RENNeg_MRSNeg, ActiveLow => true, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => RD_RENNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_RENNeg_PRSNeg ); VitalRecoveryRemovalCheck ( TestSignal => WENNegIn, TestSignalName => "WENNeg", RefSignal => PRSNegIn, RefSignalName => "PRSNeg", Recovery => trecovery_RENNeg_MRSNeg, ActiveLow => true, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => RD_WENNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_WENNeg_PRSNeg ); -- tRS VitalPeriodPulseCheck ( TestSignal => MRSNegIn, TestSignalName => "MRSNeg", PulseWidthLow => tpw_MRSNeg_negedge, HeaderMsg => InstancePath & partID, CheckEnabled => TRUE, PeriodData => PD_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_MRSNeg ); VitalPeriodPulseCheck ( TestSignal => PRSNegIn, TestSignalName => "PRSNeg", PulseWidthLow => tpw_MRSNeg_negedge, HeaderMsg => InstancePath & partID, CheckEnabled => TRUE, PeriodData => PD_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_PRSNeg ); -- tCLK1, tCLKL1, tCLKH1 VitalPeriodPulseCheck ( TestSignal => RCLKIn, TestSignalName => "RCLK", Period => tperiod_RCLK_SDR_posedge, PulseWidthLow => tpw_RCLK_SDR_negedge, PulseWidthHigh => tpw_RCLK_SDR_posedge, HeaderMsg => InstancePath & partID, CheckEnabled => mode_rd = SDR AND mreset, PeriodData => PD_RCLK1, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_RCLK1 ); VitalPeriodPulseCheck ( TestSignal => WCLKIn, TestSignalName => "WCLK", Period => tperiod_RCLK_SDR_posedge, PulseWidthLow => tpw_RCLK_SDR_negedge, PulseWidthHigh => tpw_RCLK_SDR_posedge, HeaderMsg => InstancePath & partID, CheckEnabled => mode_wr = SDR AND mreset, PeriodData => PD_WCLK1, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_WCLK1 ); -- tCLK2, tCLKL2, tCLKH2 VitalPeriodPulseCheck ( TestSignal => RCLKIn, TestSignalName => "RCLK", Period => tperiod_RCLK_DDR_posedge, PulseWidthLow => tpw_RCLK_DDR_negedge, PulseWidthHigh => tpw_RCLK_DDR_posedge, HeaderMsg => InstancePath & partID, CheckEnabled => mode_rd = DDR AND mreset, PeriodData => PD_RCLK2, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_RCLK2 ); -- tCLK2, tCLKL2, tCLKH2 VitalPeriodPulseCheck ( TestSignal => WCLKIn, TestSignalName => "WCLK", Period => tperiod_RCLK_DDR_posedge, PulseWidthLow => tpw_RCLK_DDR_negedge, PulseWidthHigh => tpw_RCLK_DDR_posedge, HeaderMsg => InstancePath & partID, CheckEnabled => mode_wr = DDR AND mreset, PeriodData => PD_WCLK2, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_WCLK2 ); -- tSCLK, tSCKH, tSCKHL VitalPeriodPulseCheck ( TestSignal => SCLKIn, TestSignalName => "SCLK", Period => tperiod_SCLK_posedge, PulseWidthLow => tpw_SCLK_negedge, PulseWidthHigh => tpw_SCLK_posedge, HeaderMsg => InstancePath & partID, CheckEnabled => true, PeriodData => PD_SCLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_SCLK ); -- tPDL VitalPeriodPulseCheck ( TestSignal => PDNegIn, TestSignalName => "PDNeg", PulseWidthLow => tpw_PDNeg_negedge, HeaderMsg => InstancePath & partID, CheckEnabled => true, PeriodData => PD_PDNeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_PDNeg ); Violation := Tviol_D_WCLK OR Tviol_D_WCLK_DDR OR Tviol_RENNeg_RCLK OR Tviol_WENNeg_WCLK OR Tviol_RCSNeg_RCLK OR Tviol_SI_SCLK OR Tviol_SWENNeg_SCLK OR Tviol_SRENNeg_SCLK OR Tviol_RENNeg_PDNeg OR Tviol_WENNeg_PDNeg OR Tviol_RENNeg_MRSNeg OR Tviol_WENNeg_MRSNeg OR Tviol_SWENNeg_MRSNeg OR Tviol_SRENNeg_MRSNeg OR Tviol_FWFT_MRSNeg OR Tviol_FSEL1_MRSNeg OR Tviol_FSEL0_MRSNeg OR Tviol_MD_MRSNeg OR Tviol_OW_MRSNeg OR Tviol_IW_MRSNeg OR Tviol_WDDR_MRSNeg OR Tviol_RDDR_MRSNeg OR Tviol_PFM_MRSNeg OR Tviol_IOSEL_MRSNeg OR Tviol_RENNeg_PRSNeg OR Tviol_WENNeg_PRSNeg OR Tviol_SWENNeg_PRSNeg OR Tviol_SRENNeg_PRSNeg OR Rviol_RENNeg_MRSNeg OR Rviol_WENNeg_MRSNeg OR Rviol_RENNeg_PRSNeg OR Rviol_WENNeg_PRSNeg OR Pviol_MRSNeg OR Pviol_PRSNeg OR Pviol_RCLK1 OR Pviol_WCLK1 OR Pviol_RCLK2 OR Pviol_WCLK2 OR Pviol_SCLK OR Pviol_PDNeg; ASSERT Violation = '0' REPORT InstancePath & partID & ": simulation may be" & " inaccurate due to timing violations" SEVERITY WARNING; END IF; ---------------------------------------------------------------------------- -- Functionality Section ---------------------------------------------------------------------------- IF falling_edge(MRSNegIn) THEN master_reset; ELSIF PRSNegIn'event AND PRSNegIn = '0' AND NOT MRSNegIn = '0' THEN partial_reset; END IF; -- skew and power down cycles counting IF rising_edge(WCLKIn) THEN tWCLKposedge := NOW; count_skew; END IF; IF falling_edge(WCLKIn) THEN tWCLKnegedge := NOW; count_skew; END IF; IF rising_edge(RCLKIn) THEN tRCLKposedge := Now; count_skew; END IF; IF falling_edge(RCLKIn) THEN tRCLKnegedge := NOW; count_skew; END IF; IF rising_edge(RENNegIn) THEN count_rcycle := 0; ELSIF rising_edge(WENNegIn) THEN count_wcycle := 0; ELSIF rising_edge(RCLKIn) AND RENNegIn = '1' THEN count_rcycle := count_rcycle +1; ELSIF rising_edge(WCLKIn) AND WENNegIn = '1' THEN count_wcycle := count_wcycle +1; END IF; --Power down IF falling_edge(PDNegIn) THEN IF count_rcycle >= 4 AND count_wcycle >= 4 THEN IF MDIn = '0' AND OWIn = '1' THEN Q_zd(19 downto 0) <= (others => 'Z'); ELSE Q_zd(9 downto 0) <= (others => 'Z'); END IF; ERENNeg_zd := 'Z'; ERCLK_zd := 'Z'; FROMPD <= '1', '0' AFTER 1 ns; ELSE REPORT "4 read and write cycles must pass before asserting PDNeg"; END IF; ELSIF rising_edge(PDNegIn) THEN Q_zd <= Qreg; END IF; -- write to fifo IF mreset AND WCLKIn'event AND PDNeg = '1' THEN IF ((FFNeg_zd = '1' AND not fwft) OR (FFNeg_zd = '0' AND fwft)) OR bm_Incnt /= 0 THEN CASE in_mode IS -- different bus-match and rate modes WHEN DDR20 => IF rising_edge(WCLKIn) AND WENNegIn = '0' AND WCSNegIn = '0' AND bm_Incnt = 0 THEN write_input; memA(wrptr) := Data2; memB(wrptr) := Data1; wrptr_next := wrptr; wrote_in := true; bm_Incnt :=bm_Incnt + 1; IF (count=0 AND fwft AND NOT(fw_done)) THEN outtmp(39 downto 20) := DIn(19 downto 0); fwcnt := 1; END IF; ELSIF bm_Incnt = 1 THEN write_input; memA(wrptr_next + TotalLoc/2) := Data2; memB(wrptr_next + TotalLoc/2) := Data1; last_done := write; bm_Incnt:=0; IF ((fwcnt=1 AND fwft) AND NOT(fw_done)) THEN outtmp(19 downto 0) := DIn(19 downto 0); do_fw := true; fwcnt := 0; END IF; END IF; WHEN SDR20 => IF out_mode = DDR20 THEN IF rising_edge(WCLKIn) AND WENNegIn = '0' AND WCSNegIn = '0' THEN IF bm_Incnt = 0 THEN write_input; memA(wrptr) := Data2; memB(wrptr) := Data1; wrptr_next := wrptr; wrote_in := true; bm_Incnt:=bm_Incnt + 1; IF (count=0 AND fwft AND NOT(fw_done)) THEN outtmp(39 downto 20) := DIn(19 downto 0); do_fw := true; fwcnt := 1; END IF; ELSIF bm_Incnt=1 THEN write_input; memA(wrptr_next + TotalLoc/2) := Data2; memB(wrptr_next + TotalLoc/2) := Data1; last_done := write; bm_Incnt:=0; IF (fwcnt=1 AND fwft) THEN outtmp(19 downto 0) := DIn(19 downto 0); fwcnt := 0; END IF; END IF; END IF; ELSE IF rising_edge(WCLKIn) AND WENNegIn = '0' AND WCSNegIn = '0' AND bm_Incnt = 0 THEN write_input; memA(wrptr) := Data2; memB(wrptr) := Data1; wrote_in := true; last_done := write; IF (count=0 AND fwft AND NOT(fw_done)) THEN outtmp(19 downto 0) := DIn(19 downto 0); do_fw := true; END IF; END IF; END IF; WHEN DDR10 => IF out_mode = DDR20 THEN IF rising_edge(WCLKIn) AND WENNegIn = '0' AND WCSNegIn = '0' AND bm_Incnt = 0 THEN write_input; memA(wrptr) := Data1; wrptr_next := wrptr; wrote_in := true; bm_Incnt:=bm_Incnt + 1; IF (count=0 AND fwft AND NOT(fw_done)) THEN outtmp(39 downto 30) := DIn(9 downto 0); fwcnt := 1; END IF; ELSIF bm_Incnt=1 THEN write_input; memB(wrptr_next) := Data1; bm_Incnt:=bm_Incnt + 1; IF (fwcnt=1 AND fwft AND NOT(fw_done)) THEN outtmp(29 downto 20) := DIn(9 downto 0); do_fw := true; fwcnt := 2; END IF; ELSIF bm_Incnt=2 THEN write_input; memA(wrptr_next + TotalLoc/2) := Data1; bm_Incnt:=bm_Incnt + 1; IF (fwcnt=2 AND fwft) THEN outtmp(19 downto 10) := DIn(9 downto 0); fwcnt := 3; END IF; ELSIF bm_Incnt=3 THEN write_input; memB(wrptr_next + TotalLoc/2) := Data1; last_done := write; bm_Incnt:=0; IF (fwcnt=3 AND fwft) THEN outtmp(9 downto 0) := DIn(9 downto 0); fwcnt := 0; END IF; END IF; ELSE IF rising_edge(WCLKIn) AND WENNegIn = '0' AND WCSNegIn = '0' AND bm_Incnt = 0 THEN write_input; memA(wrptr) := Data1; wrptr_next := wrptr; wrote_in := true; bm_Incnt:=bm_Incnt + 1; IF (count=0 AND fwft AND NOT(fw_done)) THEN outtmp(19 downto 10) := DIn(9 downto 0); fwcnt := 1; END IF; ELSIF bm_Incnt=1 THEN write_input; memB(wrptr_next) := Data1; last_done := write; bm_Incnt:=0; IF (fwcnt=1 AND fwft AND NOT(fw_done)) THEN outtmp(9 downto 0) := DIn(9 downto 0); fwcnt := 0; do_fw := true; END IF; END IF; END IF; WHEN SDR10 => IF out_mode = DDR20 THEN IF rising_edge(WCLKIn) AND WENNegIn = '0' AND WCSNegIn = '0' THEN IF bm_Incnt = 0 THEN write_input; memA(wrptr) := Data1; wrptr_next := wrptr; wrote_in := true; bm_Incnt:=bm_Incnt + 1; IF (count=0 AND fwft AND NOT(fw_done)) THEN outtmp(39 downto 30) := DIn(9 downto 0); do_fw := true; fwcnt := 1; END IF; ELSIF bm_Incnt = 1 THEN write_input; memB(wrptr_next) := Data1; bm_Incnt:=bm_Incnt + 1; IF (fwcnt=1 AND fwft) THEN outtmp(29 downto 20) := DIn(9 downto 0); fwcnt := 2; END IF; ELSIF bm_Incnt = 2 THEN write_input; memA(wrptr_next + TotalLoc/2) := Data1; bm_Incnt:=bm_Incnt + 1; IF (fwcnt=2 AND fwft) THEN outtmp(19 downto 10) := DIn(9 downto 0); fwcnt := 3; END IF; ELSIF bm_Incnt = 3 THEN write_input; memB(wrptr_next + TotalLoc/2) := Data1; last_done := write; bm_Incnt:=0; IF (fwcnt=3 AND fwft) THEN outtmp(9 downto 0) := DIn(9 downto 0); fwcnt := 0; END IF; END IF; END IF; ELSE IF rising_edge(WCLKIn) AND WENNegIn = '0' AND WCSNegIn = '0' THEN IF bm_Incnt = 0 THEN write_input; memA(wrptr) := Data1; wrptr_next := wrptr; wrote_in := true; last_done := write; bm_Incnt:=bm_Incnt + 1; IF (count=0 AND fwft AND NOT(fw_done)) THEN IF out_mode = SDR10 THEN outtmp(9 downto 0) := DIn(9 downto 0); ELSE outtmp(19 downto 10) := DIn(9 downto 0); END IF; do_fw := true; fwcnt := 1; END IF; ELSIF bm_Incnt = 1 THEN write_input; memB(wrptr_next) := Data1; IF out_mode = SDR10 THEN wrote_in := true; END IF; last_done := write; bm_Incnt:=0; IF (fwcnt=1 AND fwft AND NOT(fw_done)) THEN outtmp(9 downto 0) := DIn(9 downto 0); fwcnt := 0; IF out_mode = SDR10 THEN do_fw := true; END IF; END IF; END IF; END IF; END IF; END CASE; END IF; --- flag ctrl if just wrote in IF wrote_in THEN wrote_in := false; IF (fwft AND FFNeg_zd = '0') OR (NOT(fwft) AND FFNeg_zd = '1') THEN--not full -- write pointer IF (wrptr < TotalLoc1 -1 AND NOT(in_mode = SDR10 AND out_mode = SDR10)) THEN wrptr := wrptr + 1; ELSIF (wrptr >= TotalLoc1 -1 AND NOT(in_mode = SDR10 AND out_mode = SDR10)) THEN wrptr := 0; ELSIF (in_mode = SDR10 AND out_mode = SDR10 AND wrptr < TotalLoc1/2 - 1 AND bm_Incnt = 0) THEN wrptr := wrptr + 1; ELSIF (in_mode = SDR10 AND out_mode = SDR10 AND wrptr >= TotalLoc1/2 - 1 AND bm_Incnt = 0) THEN wrptr := 0; END IF; --counter count := count + 1; -- FFNeg sync updating IF count = TotalLoc1 THEN IF fwft THEN FFNeg_zd := '1'; ELSE FFNeg_zd := '0'; END IF; END IF; -- PAFNeg sync updating IF pafoff <= count THEN PAFNeg_dly := '0'; delayed_paf := true; ELSE PAFNeg_dly := '1'; END IF; -- flags for EFNeg and PAENeg updating IF PFM_mode = sync THEN IF (count = 1 AND NOT(fwft)) OR count = paeoff + 1 THEN wr_upd_flg := true; ELSE wr_upd_flg := false; END IF; ELSE IF count = paeoff + 1 THEN PAENeg_zd := '1'; ELSIF (count = 1 AND NOT(fwft)) THEN wr_upd_flg := true; ELSE wr_upd_flg := false; END IF; END IF; END IF; END IF; IF rising_edge(WCLKIn) THEN -- FFNeg updating when reading active IF mode_rd = DDR THEN IF NOT(minskew2RW) AND flag_FF = '1' THEN IF Fflagcnt < 1 THEN Fflagcnt := Fflagcnt + 1; ELSE IF NOT(fwft) THEN FFNeg_zd := '1'; ELSE FFNeg_zd := '0'; END IF; Fflagcnt := 0; flag_FF := '0'; END IF; ELSIF minskew2RW AND flag_FF = '1' THEN IF NOT(fwft) THEN FFNeg_zd := '1'; ELSE FFNeg_zd := '0'; END IF; Fflagcnt := 0; flag_FF := '0'; END IF; ELSE IF NOT(minskew1RW) AND flag_FF = '1' THEN IF Fflagcnt < 1 THEN Fflagcnt := Fflagcnt + 1; ELSE IF NOT(fwft) THEN FFNeg_zd := '1'; ELSE FFNeg_zd := '0'; END IF; Fflagcnt := 0; flag_FF := '0'; END IF; ELSIF minskew1RW AND flag_FF = '1' THEN IF NOT(fwft) THEN FFNeg_zd := '1'; ELSE FFNeg_zd := '0'; END IF; Fflagcnt := 0; flag_FF := '0'; END IF; END IF; -- PAFNeg updating when write active IF (write_clk_paf = 2 AND delayed_paf AND PFM_mode = sync) OR (delayed_paf AND PFM_mode = async)THEN PAFNeg_zd := PAFNeg_dly; write_clk_paf := 0; delayed_paf := false; ELSIF delayed_paf THEN write_clk_paf := write_clk_paf + 1; END IF; -- PAFNeg updating when read active IF NOT(minskew3RW) AND flag_PAF = '1' THEN IF PAFflagcnt < 1 THEN PAFflagcnt := PAFflagcnt + 1; ELSE PAFNeg_zd := '1'; PAFflagcnt := 0; flag_PAF := '0'; END IF; ELSIF minskew3RW AND flag_PAF = '1' THEN PAFNeg_zd := '1'; PAFflagcnt := 0; flag_PAF := '0'; END IF; -- FFNeg updating when read active IF rd_upd_flg AND count = TotalLoc1 - 1 THEN pass_FF := true; rd_upd_flg := false; END IF; IF last_done = read AND pass_FF THEN flag_FF := '1'; pass_FF := false; END IF; -- PAFNeg updating when read active IF rd_upd_flg AND count = pafoff - 1 THEN pass_PAF := true; rd_upd_flg := false; END IF; IF last_done = read AND pass_PAF THEN flag_PAF := '1'; pass_PAF := false; END IF; END IF; END IF; --- First Word Fall Through IF RCLKIn'event AND fwft AND PDNeg = '1' THEN IF rising_edge(RCLKIn) THEN IF (do_fw AND fwftcnt = 0 AND EFNeg_zd = '1') THEN fwftcnt := fwftcnt + 1; IF out_mode = SDR10 AND in_mode = SDR10 THEN bm_Outcnt := 1; rdptr_next := 0; ELSE rdptr := rdptr + 1; END IF; count := count -1; fw_done := true; ELSIF (do_fw AND fwftcnt = 1) THEN fwftcnt := fwftcnt + 1; ELSIF (do_fw AND fwftcnt = 2) THEN IF (minskew1WR AND mode_wr = SDR) OR (minskew2WR AND mode_wr = DDR)THEN fwftvar := true; EFNeg_zd := '0'; fwftcnt := 0; fwftcnt1 := 0; outreg := outtmp; FROMOE := false; FROMRCLK := true; do_fw := false; ELSE fwftcnt := fwftcnt + 1; END IF; ELSIF (do_fw AND fwftcnt = 3) THEN fwftvar := true; EFNeg_zd := '0'; fwftcnt := 0; fwftcnt1 := 0; outreg := outtmp; FROMOE := false; FROMRCLK := true; do_fw := false; END IF; END IF; IF fwftvar AND mode_rd = DDR THEN IF out_mode = DDR20 THEN IF fwftcnt1 = 0 THEN Qreg(19 downto 0) := outreg(39 downto 20); fwftcnt1 := 1; ELSE Qreg(19 downto 0) := outreg(19 downto 0); fwftcnt1 := 0; fwftvar := false; END IF; ELSIF out_mode = DDR10 THEN IF in_mode = DDR20 THEN IF fwftcnt1 = 0 THEN Qreg(9 downto 0) := outreg(39 downto 30); fwftcnt1 := 1; ELSIF fwftcnt1 = 1 THEN Qreg(9 downto 0) := outreg(29 downto 20); fwftcnt1 := 2; ELSIF fwftcnt1 = 2 THEN Qreg(9 downto 0) := outreg(19 downto 10); fwftcnt1 := 3; ELSIF fwftcnt1 = 3 THEN Qreg(9 downto 0) := outreg(9 downto 0); fwftcnt1 := 0; fwftvar := false; END IF; ELSE IF fwftcnt1 = 0 THEN Qreg(9 downto 0) := outreg(19 downto 10); fwftcnt1 := 1; ELSIF fwftcnt1 = 1 THEN Qreg(9 downto 0) := outreg(9 downto 0); fwftcnt1 := 0; fwftvar := false; END IF; END IF; END IF; ELSIF fwftvar AND mode_rd = SDR AND rising_edge(RCLKIn) THEN IF out_mode = SDR20 THEN IF in_mode = DDR20 THEN IF fwftcnt1 = 0 THEN Qreg(19 downto 0) := outreg(39 downto 20); fwftcnt1 := 1; ELSE Qreg(19 downto 0) := outreg(19 downto 0); fwftcnt1 := 0; fwftvar := false; END IF; ELSE Qreg(19 downto 0) := outreg(19 downto 0); fwftcnt1 := 0; fwftvar := false; END IF; ELSIF out_mode = SDR10 THEN IF in_mode = DDR20 THEN IF fwftcnt1 = 0 THEN Qreg(9 downto 0) := outreg(39 downto 30); fwftcnt1 := 1; ELSIF fwftcnt1 = 1 THEN Qreg(9 downto 0) := outreg(29 downto 20); fwftcnt1 := 2; ELSIF fwftcnt1 = 2 THEN Qreg(9 downto 0) := outreg(19 downto 10); fwftcnt1 := 3; ELSIF fwftcnt1 = 3 THEN Qreg(9 downto 0) := outreg(9 downto 0); fwftcnt1 := 0; fwftvar := false; END IF; ELSIF in_mode = SDR10 THEN Qreg(9 downto 0) := outreg(9 downto 0); fwftcnt1 := 0; fwftvar := false; ELSE IF fwftcnt1 = 0 THEN Qreg(9 downto 0) := outreg(19 downto 10); fwftcnt1 := 1; ELSIF fwftcnt1 = 1 THEN Qreg(9 downto 0) := outreg(9 downto 0); fwftcnt1 := 0; fwftvar := false; END IF; END IF; END IF; END IF; END IF; -- empty fifo in fwft mode IF count = 0 AND EFNeg_zd = '0' AND fwft AND RENNeg = '0' AND rising_edge(RCLKIn) AND RCSNeg = '0' THEN EFNeg_zd := '1'; END IF; IF mreset AND RCLKIn'EVENT THEN -- echo read clock IF PDNegIn = '1' THEN IF rising_edge(RCLKIn) THEN ERCLK_zd := '1'; ELSIF falling_edge(RCLKIn) THEN ERCLK_zd := '0'; END IF; -- echo read enable IF (((EFNeg_zd='1' AND NOT(fwft)) OR (EFNeg_zd='0' AND fwft)) AND rising_edge(RCLKIn) AND (RENNegIn='0') AND RCSNegIn='0') OR (RCLKIn'event AND fwftvar AND fwft AND RCSNeg = '1') THEN ERENNeg_zd := '0'; ELSIF (rising_edge(RCLKIn) AND last_done = read) OR (rising_edge(RCLKIn) AND RENNegIn = '1') OR (rising_edge(RCLKIn) AND (NOT fwftvar) AND fwft AND RCSNeg = '1') OR (rising_edge(RCLKIn) AND RCSNegIn = '1') THEN -- at the end of the reading cycle ERENNeg_zd := '1'; -- or if RENNeg or RCSNeg inactive END IF; END IF; -- read from fifo IF ((count > 0) AND ((EFNeg_zd = '1' AND not fwft) OR (EFNeg_zd = '0' AND fwft))) OR bm_Outcnt /= 0 THEN CASE out_mode IS WHEN DDR20 => IF rising_edge(RCLKIn) AND RENNegIn = '0' AND RCSNegIn = '0' AND bm_Outcnt = 0 THEN generate_output(rdptr); Qreg(19 downto 10) := Qreg_tmp(19 downto 10); Qreg(9 downto 0) := Qreg_tmp(9 downto 0); read_out := true; rdptr_next := rdptr; bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 1 THEN generate_output(rdptr_next + TotalLoc/2); Qreg(19 downto 10) := Qreg_tmp(19 downto 10); Qreg(9 downto 0) := Qreg_tmp(9 downto 0); last_done := read; bm_Outcnt :=0; END IF; WHEN SDR20 => IF rising_edge(RCLKIn) AND RENNegIn = '0' AND RCSNegIn = '0' THEN IF in_mode = DDR20 THEN IF bm_Outcnt = 0 THEN generate_output(rdptr); Qreg(19 downto 0) := Qreg_tmp(19 downto 0); bm_Outcnt :=bm_Outcnt + 1; rdptr_next := rdptr; ELSIF bm_Outcnt = 1 THEN generate_output(rdptr_next + TotalLoc/2); Qreg(19 downto 0) := Qreg_tmp(19 downto 0); read_out := true; last_done := read; bm_Outcnt :=0; END IF; ELSE IF bm_Outcnt = 0 THEN generate_output(rdptr); Qreg(19 downto 0) := Qreg_tmp(19 downto 0); read_out := true; last_done := read; bm_Outcnt :=0; END IF; END IF; END IF; WHEN DDR10 => IF in_mode = DDR20 THEN IF rising_edge(RCLKIn) AND RENNegIn = '0' AND RCSNegIn = '0' AND bm_Outcnt = 0 THEN generate_output(rdptr); Qreg(9 downto 0) := Qreg_tmp(19 downto 10); rdptr_next := rdptr; bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 1 THEN generate_output(rdptr_next); Qreg(9 downto 0) := Qreg_tmp(9 downto 0); bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 2 THEN generate_output(rdptr_next + TotalLoc/2); Qreg(9 downto 0) := Qreg_tmp(19 downto 10); read_out := true; bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 3 THEN generate_output(rdptr_next + TotalLoc/2); Qreg(9 downto 0) := Qreg_tmp(9 downto 0); last_done := read; bm_Outcnt :=0; END IF; ELSE IF rising_edge(RCLKIn) AND RENNegIn = '0' AND RCSNegIn = '0' AND bm_Outcnt = 0 THEN generate_output(rdptr); Qreg(9 downto 0) := Qreg_tmp(19 downto 10); read_out := true; rdptr_next := rdptr; bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 1 THEN generate_output(rdptr_next); Qreg(9 downto 0) := Qreg_tmp(9 downto 0); last_done := read; bm_Outcnt :=0; END IF; END IF; WHEN SDR10 => IF rising_edge(RCLKIn) AND RENNegIn = '0' AND RCSNegIn = '0' THEN IF in_mode = DDR20 THEN IF bm_Outcnt = 0 THEN generate_output(rdptr); Qreg(9 downto 0) := Qreg_tmp(19 downto 10); rdptr_next := rdptr; bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 1 THEN generate_output(rdptr_next); Qreg(9 downto 0) := Qreg_tmp(9 downto 0); bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 2 THEN generate_output(rdptr_next + TotalLoc/2); Qreg(9 downto 0) := Qreg_tmp(19 downto 10); bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 3 THEN generate_output(rdptr_next + TotalLoc/2); Qreg(9 downto 0) := Qreg_tmp(9 downto 0); read_out := true; last_done := read; bm_Outcnt :=0; END IF; ELSE IF bm_Outcnt = 0 THEN generate_output(rdptr); Qreg(9 downto 0) := Qreg_tmp(19 downto 10); IF in_mode = SDR10 THEN read_out := true; last_done := read; END IF; rdptr_next := rdptr; bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 1 THEN generate_output(rdptr_next); Qreg(9 downto 0) := Qreg_tmp(9 downto 0); read_out := true; last_done := read; bm_Outcnt :=0; END IF; END IF; END IF; END CASE; END IF; IF read_out THEN read_out := false; IF (fwft AND EFNeg_zd = '0') OR (not(fwft) AND EFNeg_zd = '1') THEN --not empty -- read pointer IF (rdptr < TotalLoc1 - 1 AND NOT(in_mode = SDR10 AND out_mode = SDR10)) THEN rdptr := rdptr + 1; ELSIF (rdptr >= TotalLoc1 - 1 AND NOT(in_mode = SDR10 AND out_mode = SDR10)) THEN rdptr := 0; ELSIF (in_mode = SDR10 AND out_mode = SDR10 AND rdptr < TotalLoc1/2 - 1 AND bm_Outcnt = 0) THEN rdptr := rdptr + 1; ELSIF (in_mode = SDR10 AND out_mode = SDR10 AND rdptr >= TotalLoc1/2 - 1 AND bm_Outcnt = 0) THEN rdptr := 0; END IF; -- counter count := count - 1; IF count = 0 THEN fw_done := false; END IF; -- update PAENeg, delayed IF count <= paeoff THEN PAENeg_dly := '0'; delayed_pae := true; ELSE PAENeg_dly := '1'; END IF; -- update EFNeg, for idt standard mode only IF count = 0 AND NOT(fwft) THEN EFNeg_zd := '0'; END IF; -- for updating PAFNeg and FFNeg IF PFM_mode = sync THEN IF (count = TotalLoc1 -1) OR (count = pafoff - 1) THEN rd_upd_flg := true; ELSE rd_upd_flg := false; END IF; ELSE IF (count = pafoff - 1) THEN PAFNeg_zd := '1'; ELSIF (count = TotalLoc1 -1) THEN rd_upd_flg := true; ELSE rd_upd_flg := false; END IF; END IF; END IF; END IF; IF rising_edge(RCLKIn) THEN --EFNeg updating when reading active IF mode_wr = DDR THEN IF NOT(minskew2WR) AND flag_EF = '1' THEN IF Eflagcnt < 1 THEN Eflagcnt := Eflagcnt + 1; ELSE EFNeg_zd := '1'; Eflagcnt := 0; flag_EF := '0'; END IF; ELSIF minskew2WR AND flag_EF = '1' THEN EFNeg_zd := '1'; Eflagcnt := 0; flag_EF := '0'; END IF; ELSE IF NOT(minskew1WR) AND flag_EF = '1' THEN IF NOT(fwft) THEN IF Eflagcnt < 1 THEN Eflagcnt := Eflagcnt + 1; ELSE EFNeg_zd := '1'; Eflagcnt := 0; flag_EF := '0'; END IF; END IF; ELSIF minskew1WR AND flag_EF = '1' THEN IF NOT(fwft) THEN EFNeg_zd := '1'; Eflagcnt := 0; flag_EF := '0'; END IF; END IF; END IF; --PAENeg updating when writing - delayed IF (read_clk_pae = 2 AND delayed_pae AND PFM_mode = sync) OR (delayed_pae AND PFM_mode = async) THEN --asynchronous mode PAENeg_zd := PAENeg_dly; read_clk_pae := 0; delayed_pae := false; ELSIF delayed_pae THEN read_clk_pae := read_clk_pae + 1; END IF; --PAENeg updating when write active IF NOT(minskew3WR) AND flag_PAE = '1' THEN IF PAEflagcnt < 1 THEN PAEflagcnt := PAEflagcnt + 1; ELSE PAENeg_zd := '1'; PAEflagcnt := 0; flag_PAE := '0'; END IF; ELSIF minskew3WR AND flag_PAE = '1' THEN PAENeg_zd := '1'; PAEflagcnt := 0; flag_PAE := '0'; END IF; --EFNeg updating when reading active IF wr_upd_flg AND count = 1 THEN pass_EF := true; wr_upd_flg := false; END IF; IF last_done = write AND pass_EF THEN flag_EF := '1'; pass_EF := false; END IF; --PAENeg updating when write active IF wr_upd_flg AND count = paeoff + 1 THEN pass_PAE := true; wr_upd_flg := false; END IF; IF last_done = write AND pass_PAE THEN flag_PAE := '1'; pass_PAE := false; END IF; END IF; END IF; IF (rising_edge(SWENNegIn) OR rising_edge(SRENNegIn)) AND PDNegIn = '1' THEN fs_Incnt := 0; END IF; -- write to offset registers and read from them IF SWENNegIn='0' AND NOT SRENNegIn='0' AND mreset AND PDNegIn = '1' THEN write_register; ELSIF SRENNegIn='0' AND NOT SWENNegIn='0' AND mreset AND PDNegIn = '1' THEN read_register; END IF; -- path delay resolving IF falling_edge(OENegIn) THEN tOEnegedge := Now; FROMOE := false; IF time_flag_for_OE = '1' THEN IF (tpd_RCLK_Q0(tr01) - (tOEnegedge - tRCLKposedge)) >= tpd_OENeg_Q0(tr01) THEN FROMOE := false; FROMRCLK := true; ELSE FROMOE := true; FROMRCLK := false; END IF; ELSE FROMOE := true; FROMRCLK := false; END IF; END IF; -- OENeg IF mreset THEN IF OENegIn = '0' AND RCSNeg = '0' AND PDNegIn = '1' THEN IF OWIn = '1' THEN Q_zd <= Qreg; ELSE Q_zd(9 downto 0) <= Qreg(9 downto 0); END IF; ELSIF OENegIn = '1' OR (RCSNeg = '1' AND rising_edge(RCLKIn)) THEN Q_zd <= (others => 'Z'); END IF; END IF; ---------------------------------------------------------------------------- -- Path Delay Section ---------------------------------------------------------------------------- VitalPathDelay01Z ( OutSignal => ERCLKOut, OutSignalName => "ERCLK", OutTemp => ERCLK_zd, Mode => VitalTransport, GlitchData => ERCLK_GlitchData, Paths => ( 0 => (InputChangeTime => RCLKIn'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_RCLK_ERCLK), PathCondition => PDNegIn /= '0'), 1 => (InputChangeTime => PDNEgIn'LAST_EVENT, PathDelay => tpd_PDNeg_Q0, PathCondition => PDNegIn = '0') ) ); VitalPathDelay01Z ( OutSignal => SDOOut, OutSignalName => "SDO", OutTemp => SDO_zd, Paths => ( 0 => (InputChangeTime => SCLK'LAST_EVENT, PathDelay => tpd_RCLK_Q0, PathCondition => TRUE) ), GlitchData => SDO_GlitchData ); VitalPathDelay01Z ( OutSignal => ERENNegOut, OutSignalName => "ERENNeg", OutTemp => ERENNeg_zd, GlitchData => ERENNeg_GlitchData, Paths => ( 0 => (InputChangeTime => RCLKIn'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_RCLK_ERENNeg), PathCondition => PDNegIn /= '0'), 1 => (InputChangeTime => PDNEgIn'LAST_EVENT, PathDelay => tpd_PDNeg_Q0, PathCondition => PDNegIn = '0') ) ); VitalPathDelay01 ( OutSignal => EFNegOut, OutSignalName => "EFNeg", OutTemp => EFNeg_zd, GlitchData => EFNeg_GlitchData, Paths => ( 0 => (InputChangeTime => MRSNegIn'LAST_EVENT, PathDelay => tpd_MRSNeg_EFNeg, PathCondition => true), 1 => (InputChangeTime => PRSNegIn'LAST_EVENT, PathDelay => tpd_MRSNeg_EFNeg, PathCondition => true), 2 => (InputChangeTime => RCLKIn'LAST_EVENT, PathDelay => tpd_RCLK_EFNeg, PathCondition => true) ) ); VitalPathDelay01 ( OutSignal => FFNegOut, OutSignalName => "FFNeg", OutTemp => FFNeg_zd, GlitchData => FFNeg_GlitchData, Paths => ( 0 => (InputChangeTime => MRSNegIn'LAST_EVENT, PathDelay => tpd_MRSNeg_EFNeg, PathCondition => true), 1 => (InputChangeTime => PRSNegIn'LAST_EVENT, PathDelay => tpd_MRSNeg_EFNeg, PathCondition => true), 2 => (InputChangeTime => WCLKIn'LAST_EVENT, PathDelay => tpd_WCLK_FFNeg, PathCondition => true) ) ); VitalPathDelay01 ( OutSignal => PAENegOut, OutSignalName => "PAENeg", OutTemp => PAENeg_zd, GlitchData => PAENeg_GlitchData, Paths => ( 0 => (InputChangeTime => MRSNegIn'LAST_EVENT, PathDelay => tpd_MRSNeg_EFNeg, PathCondition => true), 1 => (InputChangeTime => PRSNegIn'LAST_EVENT, PathDelay => tpd_MRSNeg_EFNeg, PathCondition => true), 2 => (InputChangeTime => RCLKIn'LAST_EVENT, PathDelay => tpd_RCLK_PAENeg_sync, PathCondition => PFM_mode = sync), 3 => (InputChangeTime => WCLKIn'LAST_EVENT, PathDelay => tpd_RCLK_PAENeg_async, PathCondition => PFM_mode = async), 4 => (InputChangeTime => RCLKIn'LAST_EVENT, PathDelay => tpd_RCLK_PAENeg_async, PathCondition => PFM_mode = async) ) ); VitalPathDelay01 ( OutSignal => PAFNegOut, OutSignalName => "PAFNeg", OutTemp => PAFNeg_zd, GlitchData => PAFNeg_GlitchData, Paths => ( 0 => (InputChangeTime => MRSNegIn'LAST_EVENT, PathDelay => tpd_MRSNeg_EFNeg, PathCondition => true), 1 => (InputChangeTime => PRSNegIn'LAST_EVENT, PathDelay => tpd_MRSNeg_EFNeg, PathCondition => true), 2 => (InputChangeTime => WCLKIn'LAST_EVENT, PathDelay => tpd_WCLK_PAFNeg_sync, PathCondition => PFM_mode = sync), 3 => (InputChangeTime => RCLKIn'LAST_EVENT, PathDelay => tpd_WCLK_PAFNeg_async, PathCondition