FMF Timing for s25fl01gs Parts version: | author: | mod date: | changes made: V1.0 R. Prokopovic 23 Nov 09 Initial release V1.1 H.Dimitrijevic 03 Nov 10 Latest datasheet aligned 1ns s25fl01gs S25FL01GS00UX_WB_F_30pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS01UX_WB_F_30pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS00HT_WB_F_30pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS01HT_WB_F_30pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS00HB_WB_F_30pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS01HB_WB_F_30pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS00UX_MX_F_30pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS01UX_MX_F_30pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS00HT_MX_F_30pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS01HT_MX_F_30pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS00HB_MX_F_30pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS01HB_MX_F_30pF Spansion, S25FL128 256 512 01GS MRS The values listed are for VCC=2.7V to 3.6V, CL=30pF, Industrial Ta=-40 to +85 Celsius (DELAY (ABSOLUTE (COND ~ddr && ~glitch (IOPATH SCK SO (5.4:6.7:8) (5.4:6.7:8) () (5.4:6.7:8) () (5.4:6.7:8))) (COND dual && ~ddr (IOPATH SCK SI (5.4:6.7:8) (5.4:6.7:8) () (5.4:6.7:8) () (5.4:6.7:8))) (COND ~glitch && dual && ddr (IOPATH SCK SI (1.5:4:6.5) (1.5:4:6.5) () (1.5:4:6.5) () (1.5:4:6.5))) (COND ~glitch && (ddr || rd_fast || ddr_fast) (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) () (1.5:4:6.5) () (1.5:4:6.5))) (COND CSNeg (IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND ~QUAD (IOPATH HOLDNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))) (COND ~QUAD && dual (IOPATH HOLDNeg SI () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))) (COND ~ddr && QUAD (IOPATH SCK HOLDNeg (5.4:6.7:8) (5.4:6.7:8) () (5.4:6.7:8) () (5.4:6.7:8))) (COND ~ddr && QUAD (IOPATH SCK WPNeg (5.4:6.7:8) (5.4:6.7:8) () (5.4:6.7:8) () (5.4:6.7:8))) (COND CSNeg && dual (IOPATH CSNeg SI () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg && QUAD (IOPATH CSNeg HOLDNeg () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg && QUAD (IOPATH CSNeg WPNeg () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND ~glitch && ddr && QUAD (IOPATH SCK HOLDNeg (1.5:4:6.5) (1.5:4:6.5) () (1.5:4:6.5) () (1.5:4:6.5))) (COND ~glitch && ddr && QUAD (IOPATH SCK WPNeg (1.5:4:6.5) (1.5:4:6.5) () (1.5:4:6.5) () (1.5:4:6.5))) (IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8)) )) (TIMINGCHECK (SETUP CSNeg SCK (3)) (SETUP SI (COND deg_sin(posedge SCK)) (3)) (SETUP SI (COND ddro(posedge SCK)) (1.5)) (SETUP SI (COND ddro(negedge SCK)) (1.5)) (SETUP WPNeg (COND wr_prot(negedge CSNeg)) (20)) (SETUP HOLDNeg (COND quad_rd (posedge SCK)) (2)) (SETUP RSTNeg CSNeg (200)) (HOLD CSNeg SCK (3)) (HOLD SI (COND deg_sin (posedge SCK)) (2)) (HOLD SI (COND ddro (posedge SCK)) (1.5)) (HOLD SI (COND ddro (negedge SCK)) (1.5)) (HOLD WPNeg (COND wr_prot (posedge CSNeg)) (100)) (HOLD HOLDNeg (COND quad_rd (posedge SCK)) (2)) (HOLD CSNeg RSTNeg (35000)) (WIDTH (COND rd (posedge SCK)) (10)) (WIDTH (COND rd (negedge SCK)) (10)) (WIDTH (COND dual_rd (posedge SCK)) (4.8)) (WIDTH (COND dual_rd (negedge SCK)) (4.8)) (WIDTH (COND fast_rd (negedge SCK)) (3.75)) (WIDTH (COND fast_rd (posedge SCK)) (3.75)) (WIDTH (COND ddrd (posedge SCK)) (6.25)) (WIDTH (COND ddrd (negedge SCK)) (6.25)) (WIDTH (COND rd (posedge CSNeg)) (10)) (WIDTH (posedge CSNeg) (50)) (WIDTH (negedge RSTNeg) (200)) (PERIOD (COND rd SCK) (20)) (PERIOD (COND fast_rd SCK) (7.52)) (PERIOD (COND dual_rd SCK) (9.6)) (PERIOD (COND ddrd SCK) (12.5)) ) S25FL01GS00UX_WB_R_30pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS01UX_WB_R_30pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS00HT_WB_R_30pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS01HT_WB_R_30pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS00HB_WB_R_30pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS01HB_WB_R_30pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS00UX_MX_R_30pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS01UX_MX_R_30pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS00HT_MX_R_30pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS01HT_MX_R_30pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS00HB_MX_R_30pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS01HB_MX_R_30pF Spansion, S25FL128 256 512 01GS MRS The values listed are for regulated Vcc range VCC=3.0V to 3.6V, CL=30pF, Industrial Ta=-40 to +85 Celsius (DELAY (ABSOLUTE (COND ~ddr && ~glitch (IOPATH SCK SO (4.3:6.0:7.65) (4.3:6.0:7.65) () (4.3:6.0:7.65) () (4.3:6.0:7.65))) (COND dual && ~ddr (IOPATH SCK SI (4.3:6.0:7.65) (4.3:6.0:7.65) () (4.3:6.0:7.65) () (4.3:6.0:7.65))) (COND ~glitch && dual && ddr (IOPATH SCK SI (1.5:4:6.5) (1.5:4:6.5) () (1.5:4:6.5) () (1.5:4:6.5))) (COND ~glitch && (ddr || rd_fast || ddr_fast) (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) () (1.5:4:6.5) () (1.5:4:6.5))) (COND CSNeg (IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND ~QUAD (IOPATH HOLDNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))) (COND ~QUAD && dual (IOPATH HOLDNeg SI () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))) (COND ~ddr && QUAD (IOPATH SCK HOLDNeg (4.3:6.0:7.65) (4.3:6.0:7.65) () (4.3:6.0:7.65) () (4.3:6.0:7.65))) (COND ~ddr && QUAD (IOPATH SCK WPNeg (4.3:6.0:7.65) (4.3:6.0:7.65) () (4.3:6.0:7.65) () (4.3:6.0:7.65))) (COND CSNeg && dual (IOPATH CSNeg SI () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg && QUAD (IOPATH CSNeg HOLDNeg () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg && QUAD (IOPATH CSNeg WPNeg () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND ~glitch && ddr && QUAD (IOPATH SCK HOLDNeg (1.5:4:6.5) (1.5:4:6.5) () (1.5:4:6.5) () (1.5:4:6.5))) (COND ~glitch && ddr && QUAD (IOPATH SCK WPNeg (1.5:4:6.5) (1.5:4:6.5) () (1.5:4:6.5) () (1.5:4:6.5))) (IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8)) )) (TIMINGCHECK (SETUP CSNeg SCK (3)) (SETUP SI (COND deg_sin(posedge SCK)) (3)) (SETUP SI (COND ddro(posedge SCK)) (1.5)) (SETUP SI (COND ddro(negedge SCK)) (1.5)) (SETUP WPNeg (COND wr_prot(negedge CSNeg)) (20)) (SETUP HOLDNeg (COND quad_rd (posedge SCK)) (2)) (SETUP RSTNeg CSNeg (200)) (HOLD CSNeg SCK (3)) (HOLD SI (COND deg_sin (posedge SCK)) (2)) (HOLD SI (COND ddro (posedge SCK)) (1.5)) (HOLD SI (COND ddro (negedge SCK)) (1.5)) (HOLD WPNeg (COND wr_prot (posedge CSNeg)) (100)) (HOLD HOLDNeg (COND quad_rd (posedge SCK)) (2)) (HOLD CSNeg RSTNeg (35000)) (WIDTH (COND rd (posedge SCK)) (10)) (WIDTH (COND rd (negedge SCK)) (10)) (WIDTH (COND dual_rd (posedge SCK)) (4.8)) (WIDTH (COND dual_rd (negedge SCK)) (4.8)) (WIDTH (COND fast_rd (negedge SCK)) (3.75)) (WIDTH (COND fast_rd (posedge SCK)) (3.75)) (WIDTH (COND ddrd (posedge SCK)) (6.25)) (WIDTH (COND ddrd (negedge SCK)) (6.25)) (WIDTH (COND rd (posedge CSNeg)) (10)) (WIDTH (posedge CSNeg) (50)) (WIDTH (negedge RSTNeg) (200)) (PERIOD (COND rd SCK) (20)) (PERIOD (COND fast_rd SCK) (7.52)) (PERIOD (COND dual_rd SCK) (9.6)) (PERIOD (COND ddrd SCK) (12.5)) ) S25FL01GS00UX_WB_R_15pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS01UX_WB_R_15pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS00HT_WB_R_15pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS01HT_WB_R_15pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS00HB_WB_R_15pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS01HB_WB_R_15pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS00UX_MX_R_15pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS01UX_MX_R_15pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS00HT_MX_R_15pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS01HT_MX_R_15pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS00HB_MX_R_15pF Spansion, S25FL128 256 512 01GS MRS S25FL01GS01HB_MX_R_15pF Spansion, S25FL128 256 512 01GS MRS The values listed are for regulated Vcc range VCC=3.0V to 3.6V, CL=15pF, Industrial Ta=-40 to +85 Celsius (DELAY (ABSOLUTE (COND ~ddr && ~glitch (IOPATH SCK SO (4.5:5.5:6.5) (4.5:5.5:6.5) () (4.5:5.5:6.5) () (4.5:5.5:6.5))) (COND dual && ~ddr (IOPATH SCK SI (4.5:5.5:6.5) (4.5:5.5:6.5) () (4.5:5.5:6.5) () (4.5:5.5:6.5))) (COND ~glitch && dual && ddr (IOPATH SCK SI (1.5:4:6.5) (1.5:4:6.5) () (1.5:4:6.5) () (1.5:4:6.5))) (COND ~glitch && (ddr || rd_fast || ddr_fast) (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) () (1.5:4:6.5) () (1.5:4:6.5))) (COND CSNeg (IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND ~QUAD (IOPATH HOLDNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))) (COND ~QUAD && dual (IOPATH HOLDNeg SI () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))) (COND ~ddr && QUAD (IOPATH SCK HOLDNeg (4.5:5.5:6.5) (4.5:5.5:6.5) () (4.5:5.5:6.5) () (4.5:5.5:6.5))) (COND ~ddr && QUAD (IOPATH SCK WPNeg (4.5:5.5:6.5) (4.5:5.5:6.5) () (4.5:5.5:6.5) () (4.5:5.5:6.5))) (COND CSNeg && dual (IOPATH CSNeg SI () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg && QUAD (IOPATH CSNeg HOLDNeg () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg && QUAD (IOPATH CSNeg WPNeg () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND ~glitch && ddr && QUAD (IOPATH SCK HOLDNeg (1.5:4:6.5) (1.5:4:6.5) () (1.5:4:6.5) () (1.5:4:6.5))) (COND ~glitch && ddr && QUAD (IOPATH SCK WPNeg (1.5:4:6.5) (1.5:4:6.5) () (1.5:4:6.5) () (1.5:4:6.5))) (IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8)) )) (TIMINGCHECK (SETUP CSNeg SCK (3)) (SETUP SI (COND deg_sin(posedge SCK)) (3)) (SETUP SI (COND ddro(posedge SCK)) (1.5)) (SETUP SI (COND ddro(negedge SCK)) (1.5)) (SETUP WPNeg (COND wr_prot(negedge CSNeg)) (20)) (SETUP HOLDNeg (COND quad_rd (posedge SCK)) (2)) (SETUP RSTNeg CSNeg (200)) (HOLD CSNeg SCK (3)) (HOLD SI (COND deg_sin (posedge SCK)) (2)) (HOLD SI (COND ddro (posedge SCK)) (1.5)) (HOLD SI (COND ddro (negedge SCK)) (1.5)) (HOLD WPNeg (COND wr_prot (posedge CSNeg)) (100)) (HOLD HOLDNeg (COND quad_rd (posedge SCK)) (2)) (HOLD CSNeg RSTNeg (35000)) (WIDTH (COND rd (posedge SCK)) (10)) (WIDTH (COND rd (negedge SCK)) (10)) (WIDTH (COND dual_rd (posedge SCK)) (4.8)) (WIDTH (COND dual_rd (negedge SCK)) (4.8)) (WIDTH (COND fast_rd (negedge SCK)) (3.75)) (WIDTH (COND fast_rd (posedge SCK)) (3.75)) (WIDTH (COND ddrd (posedge SCK)) (6.25)) (WIDTH (COND ddrd (negedge SCK)) (6.25)) (WIDTH (COND rd (posedge CSNeg)) (10)) (WIDTH (posedge CSNeg) (50)) (WIDTH (negedge RSTNeg) (200)) (PERIOD (COND rd SCK) (20)) (PERIOD (COND fast_rd SCK) (7.52)) (PERIOD (COND dual_rd SCK) (9.6)) (PERIOD (COND ddrd SCK) (12.5)) )