FMF Timing for s25fs128s Parts version: | author: | mod date: | changes made: V1.0 V.Mancev 13 Feb 08 Initial release 1ns s25fs128s S25FS128SAGMFI000_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFI001_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFI003_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFI100_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFI101_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFI103_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFI500_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFI501_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFI503_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFV000_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFV001_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFV003_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFV100_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFV101_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFV103_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFV500_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFV501_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFV503_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGNFI000_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGNFI001_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGNFI003_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGNFI400_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGNFI401_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGNFI403_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGBHI300_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGBHI303_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGBVI300_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGBVI303_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFI000_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFI001_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFI003_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFI100_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFI101_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFI103_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFI500_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFI501_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFI503_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFV000_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFV001_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFV003_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFV100_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFV101_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFV103_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFV500_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFV501_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFV503_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSNFI000_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSNFI001_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSNFI003_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSNFI400_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSNFI401_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSNFI403_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSBHI300_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSBHI303_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSBVI300_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSBVI303_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGBHIY00_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGBHIY03_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSBHIY00_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSBHIY03_F_30pF Spansion, FS-S_DRS_V3.1, August 10, 2012 The values listed are for Industrial TA= -40 to +85 Celsius, VDD=1.7V to 2.0V, CL=30pF (DELAY (ABSOLUTE (COND rd_slow && ~glitch (IOPATH SCK SO (5.4:6.7:8) (5.4:6.7:8) (1) (5.4:6.7:8) (1) (5.4:6.7:8))) (COND (ddr || rd_fast) && ~glitch (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND dual && ~glitch (IOPATH SCK SI (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND QUAD && ~CSNeg && ~glitch (IOPATH SCK RESETNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND QUAD && ~glitch (IOPATH SCK WPNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND CSNeg && ~rst_quad (IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg && rst_quad (IOPATH CSNeg SO () () (12:16:20) () (12:16:20) ())) (COND CSNeg && dual && ~rst_quad (IOPATH CSNeg SI () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg && dual && rst_quad (IOPATH CSNeg SI () () (12:16:20) () (12:16:20) ())) (COND CSNeg && ~rst_quad (IOPATH CSNeg RESETNeg () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg && rst_quad (IOPATH CSNeg RESETNeg () () (12:16:20) () (12:16:20) ())) (COND CSNeg && ~rst_quad (IOPATH CSNeg WPNeg () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg && rst_quad (IOPATH CSNeg WPNeg () () (12:16:20) () (12:16:20) ())) )) (TIMINGCHECK (SETUP CSNeg SCK (2)) (SETUP SI (COND sdro_io1 (posedge SCK)) (2)) (SETUP SI (COND ddro_io1 (posedge SCK)) (1.5)) (SETUP SI (COND ddro_io1 (negedge SCK)) (1.5)) (SETUP SO (COND sdro_quad_io0 (posedge SCK)) (2)) (SETUP SO (COND ddro_quad_io0 (posedge SCK)) (1.5)) (SETUP SO (COND ddro_quad_io0 (negedge SCK)) (1.5)) (SETUP WPNeg (COND sdro_quad_io2 (posedge SCK)) (2)) (SETUP WPNeg (COND ddro_quad_io2 (posedge SCK)) (1.5)) (SETUP WPNeg (COND ddro_quad_io2 (negedge SCK)) (1.5)) (SETUP RESETNeg (COND sdro_quad_io3 (posedge SCK)) (2)) (SETUP RESETNeg (COND ddro_quad_io3 (posedge SCK)) (1.5)) (SETUP RESETNeg (COND ddro_quad_io3 (negedge SCK)) (1.5)) (SETUP WPNeg (COND wr_prot (negedge CSNeg)) (20)) (SETUP RESETNeg (COND rst_not_quad CSNeg) (50)) (HOLD CSNeg SCK (3)) (HOLD SI (COND sdro_io1 (posedge SCK)) (3)) (HOLD SI (COND ddro_io1 (posedge SCK)) (1.5)) (HOLD SI (COND ddro_io1 (negedge SCK)) (1.5)) (HOLD SO (COND sdro_quad_io0 (posedge SCK)) (3)) (HOLD SO (COND ddro_quad_io0 (posedge SCK)) (1.5)) (HOLD SO (COND ddro_quad_io0 (negedge SCK)) (1.5)) (HOLD WPNeg (COND sdro_quad_io2 (posedge SCK)) (3)) (HOLD WPNeg (COND ddro_quad_io2 (posedge SCK)) (1.5)) (HOLD WPNeg (COND ddro_quad_io2 (negedge SCK)) (1.5)) (HOLD RESETNeg (COND sdro_quad_io3 (posedge SCK)) (3)) (HOLD RESETNeg (COND ddro_quad_io3 (posedge SCK)) (1.5)) (HOLD RESETNeg (COND ddro_quad_io3 (negedge SCK)) (1.5)) (HOLD WPNeg (COND wr_prot (posedge CSNeg)) (100)) (HOLD CSNeg (COND reset_act (negedge RESETNeg)) (35000)) (WIDTH (COND rd (posedge SCK)) (10)) (WIDTH (COND rd (negedge SCK)) (10)) (WIDTH (COND fast_rd (negedge SCK)) (3.75)) (WIDTH (COND fast_rd (posedge SCK)) (3.75)) (WIDTH (COND ddrd (posedge SCK)) (6.25)) (WIDTH (COND ddrd (negedge SCK)) (6.25)) (WIDTH (COND RD_EQU_1 (posedge CSNeg)) (10)) (WIDTH (COND QRD_EQU_1 (posedge CSNeg)) (20)) (WIDTH (COND RD_EQU_0 (posedge CSNeg)) (50)) (WIDTH (COND reset_act (negedge RESETNeg)) (200)) (WIDTH (COND reset_act (posedge RESETNeg)) (50)) (PERIOD (COND rd SCK) (20)) (PERIOD (COND fast_rd SCK) (7.52)) (PERIOD (COND ddrd SCK) (12.5)) )) (CELL (CELLTYPE "BUFFER") (INSTANCE %LABEL%/BUF_DOutZ) (DELAY (ABSOLUTE (DEVICE OUT (1))))) (CELL (CELLTYPE "BUFFER") (INSTANCE %LABEL%/BUF_DOut) (DELAY (ABSOLUTE (DEVICE OUT (1.5:4:6.5)))) S25FS128SAGMFI000_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFI001_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFI003_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFI100_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFI101_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFI103_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFI500_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFI501_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFI503_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFV000_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFV001_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFV003_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFV100_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFV101_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFV103_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFV500_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFV501_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGMFV503_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGNFI000_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGNFI001_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGNFI003_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGNFI400_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGNFI401_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGNFI403_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGBHI300_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGBHI303_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGBVI300_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGBVI303_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFI000_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFI001_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFI003_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFI100_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFI101_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFI103_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFI500_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFI501_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFI503_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFV000_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFV001_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFV003_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFV100_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFV101_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFV103_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFV500_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFV501_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSMFV503_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSNFI000_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSNFI001_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSNFI003_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSNFI400_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSNFI401_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSNFI403_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSBHI300_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSBHI303_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSBVI300_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSBVI303_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGBHIY00_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SAGBHIY03_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSBHIY00_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 S25FS128SDSBHIY03_F_15pF Spansion, FS-S_DRS_V3.1, August 10, 2012 The values listed are for Industrial TA= -40 to +85 Celsius, VDD=1.7V to 2.0V, CL=15pF (DELAY (ABSOLUTE (COND rd_slow && ~glitch (IOPATH SCK SO (4:5:6) (4:5:6) (1) (4:5:6) (1) (4:5:6))) (COND (ddr || rd_fast) && ~glitch (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND dual && ~glitch (IOPATH SCK SI (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND QUAD && ~CSNeg && ~glitch (IOPATH SCK RESETNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND QUAD && ~glitch (IOPATH SCK WPNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND CSNeg && ~rst_quad (IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg && rst_quad (IOPATH CSNeg SO () () (12:16:20) () (12:16:20) ())) (COND CSNeg && dual && ~rst_quad (IOPATH CSNeg SI () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg && dual && rst_quad (IOPATH CSNeg SI () () (12:16:20) () (12:16:20) ())) (COND CSNeg && ~rst_quad (IOPATH CSNeg RESETNeg () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg && rst_quad (IOPATH CSNeg RESETNeg () () (12:16:20) () (12:16:20) ())) (COND CSNeg && ~rst_quad (IOPATH CSNeg WPNeg () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg && rst_quad (IOPATH CSNeg WPNeg () () (12:16:20) () (12:16:20) ())) )) (TIMINGCHECK (SETUP CSNeg SCK (2)) (SETUP SI (COND sdro_io1 (posedge SCK)) (2)) (SETUP SI (COND ddro_io1 (posedge SCK)) (1.5)) (SETUP SI (COND ddro_io1 (negedge SCK)) (1.5)) (SETUP SO (COND sdro_quad_io0 (posedge SCK)) (2)) (SETUP SO (COND ddro_quad_io0 (posedge SCK)) (1.5)) (SETUP SO (COND ddro_quad_io0 (negedge SCK)) (1.5)) (SETUP WPNeg (COND sdro_quad_io2 (posedge SCK)) (2)) (SETUP WPNeg (COND ddro_quad_io2 (posedge SCK)) (1.5)) (SETUP WPNeg (COND ddro_quad_io2 (negedge SCK)) (1.5)) (SETUP RESETNeg (COND sdro_quad_io3 (posedge SCK)) (2)) (SETUP RESETNeg (COND ddro_quad_io3 (posedge SCK)) (1.5)) (SETUP RESETNeg (COND ddro_quad_io3 (negedge SCK)) (1.5)) (SETUP WPNeg (COND wr_prot (negedge CSNeg)) (20)) (SETUP RESETNeg (COND rst_not_quad CSNeg) (50)) (HOLD CSNeg SCK (3)) (HOLD SI (COND sdro_io1 (posedge SCK)) (3)) (HOLD SI (COND ddro_io1 (posedge SCK)) (1.5)) (HOLD SI (COND ddro_io1 (negedge SCK)) (1.5)) (HOLD SO (COND sdro_quad_io0 (posedge SCK)) (3)) (HOLD SO (COND ddro_quad_io0 (posedge SCK)) (1.5)) (HOLD SO (COND ddro_quad_io0 (negedge SCK)) (1.5)) (HOLD WPNeg (COND sdro_quad_io2 (posedge SCK)) (3)) (HOLD WPNeg (COND ddro_quad_io2 (posedge SCK)) (1.5)) (HOLD WPNeg (COND ddro_quad_io2 (negedge SCK)) (1.5)) (HOLD RESETNeg (COND sdro_quad_io3 (posedge SCK)) (3)) (HOLD RESETNeg (COND ddro_quad_io3 (posedge SCK)) (1.5)) (HOLD RESETNeg (COND ddro_quad_io3 (negedge SCK)) (1.5)) (HOLD WPNeg (COND wr_prot (posedge CSNeg)) (100)) (HOLD CSNeg (COND reset_act (negedge RESETNeg)) (35000)) (WIDTH (COND rd (posedge SCK)) (10)) (WIDTH (COND rd (negedge SCK)) (10)) (WIDTH (COND fast_rd (negedge SCK)) (3.75)) (WIDTH (COND fast_rd (posedge SCK)) (3.75)) (WIDTH (COND ddrd (posedge SCK)) (6.25)) (WIDTH (COND ddrd (negedge SCK)) (6.25)) (WIDTH (COND RD_EQU_1 (posedge CSNeg)) (10)) (WIDTH (COND QRD_EQU_1 (posedge CSNeg)) (20)) (WIDTH (COND RD_EQU_0 (posedge CSNeg)) (50)) (WIDTH (COND reset_act (negedge RESETNeg)) (200)) (WIDTH (COND reset_act (posedge RESETNeg)) (50)) (PERIOD (COND rd SCK) (20)) (PERIOD (COND fast_rd SCK) (7.52)) (PERIOD (COND ddrd SCK) (12.5)) )) (CELL (CELLTYPE "BUFFER") (INSTANCE %LABEL%/BUF_DOutZ) (DELAY (ABSOLUTE (DEVICE OUT (1))))) (CELL (CELLTYPE "BUFFER") (INSTANCE %LABEL%/BUF_DOut) (DELAY (ABSOLUTE (DEVICE OUT (1.5:4:6.5))))