FMF Timing for mt47h128m8 Parts version: | author: | mod date: | changes made: V1.0 D.Randjelovic 06 Mar 15 Initial release 1ns mt47h128m8 MT47H128M8BT-3Micron Technology Inc, pdf:09005aef8117c1b1, source:09005aef8117c192 1GbDDR2_2.fm - Rev. H 11/05 EN MT47H128M8BT-3ITMicron Technology Inc, pdf:09005aef8117c1b1, source:09005aef8117c192 1GbDDR2_2.fm - Rev. H 11/05 EN MT47H128M8BT-3LMicron Technology Inc, pdf:09005aef8117c1b1, source:09005aef8117c192 1GbDDR2_2.fm - Rev. H 11/05 EN MT47H128M8BT-3LITMicron Technology Inc, pdf:09005aef8117c1b1, source:09005aef8117c192 1GbDDR2_2.fm - Rev. H 11/05 EN The values listed are for VDD = +1.8V ±0.1V (DELAY (ABSOLUTE (IOPATH CK DQ0 (0.45) (0.45) (0.45) (0.45) (0.45) (0.45)) (IOPATH CK DQ1 (0.45) (0.45) (0.45) (0.45) (0.45) (0.45)) (IOPATH CK DQ2 (0.45) (0.45) (0.45) (0.45) (0.45) (0.45)) (IOPATH CK DQ3 (0.45) (0.45) (0.45) (0.45) (0.45) (0.45)) (IOPATH CK DQ4 (0.45) (0.45) (0.45) (0.45) (0.45) (0.45)) (IOPATH CK DQ5 (0.45) (0.45) (0.45) (0.45) (0.45) (0.45)) (IOPATH CK DQ6 (0.45) (0.45) (0.45) (0.45) (0.45) (0.45)) (IOPATH CK DQ7 (0.45) (0.45) (0.45) (0.45) (0.45) (0.45)) (IOPATH CK DQS (0.4) (0.4) (0.4) (0.4) (0.4) (0.4)) (IOPATH CK RDQS (0.4) (0.4) (0.4) (0.4) (0.4) (0.4)) (IOPATH CK DQSNeg (0.4) (0.4) (0.4) (0.4) (0.4) (0.4)) (IOPATH CK RDQSNeg (0.4) (0.4) (0.4) (0.4) (0.4) (0.4)) )) (TIMINGCHECK (SETUP DQ0 DQS (0.1)) (SETUP DQ1 DQS (0.1)) (SETUP DQ2 DQS (0.1)) (SETUP DQ3 DQS (0.1)) (SETUP DQ4 DQS (0.1)) (SETUP DQ5 DQS (0.1)) (SETUP DQ6 DQS (0.1)) (SETUP DQ7 DQS (0.1)) (SETUP DQ0 DQSNeg (0.1)) (SETUP DQ1 DQSNeg (0.1)) (SETUP DQ2 DQSNeg (0.1)) (SETUP DQ3 DQSNeg (0.1)) (SETUP DQ4 DQSNeg (0.1)) (SETUP DQ5 DQSNeg (0.1)) (SETUP DQ6 DQSNeg (0.1)) (SETUP DQ7 DQSNeg (0.1)) (SETUP RDQS DQS (0.1)) (SETUP RDQS DQSNeg (0.1)) (SETUP ODT CK (0.2)) (SETUP CKE CK (0.2)) (SETUP CSNeg CK (0.2)) (SETUP RASNeg CK (0.2)) (SETUP CASNeg CK (0.2)) (SETUP WENeg CK (0.2)) (SETUP BA0 CK (0.2)) (SETUP BA1 CK (0.2)) (SETUP BA2 CK (0.2)) (SETUP A0 CK (0.2)) (SETUP A1 CK (0.2)) (SETUP A2 CK (0.2)) (SETUP A3 CK (0.2)) (SETUP A4 CK (0.2)) (SETUP A5 CK (0.2)) (SETUP A6 CK (0.2)) (SETUP A7 CK (0.2)) (SETUP A8 CK (0.2)) (SETUP A9 CK (0.2)) (SETUP A10 CK (0.2)) (SETUP A11 CK (0.2)) (SETUP A12 CK (0.2)) (SETUP A13 CK (0.2)) (SETUP DQS (COND ChSetup_DSIn_CK3 CK) (0.6)) (SETUP DQS (COND ChSetup_DSIn_CK4 CK) (0.75)) (SETUP DQS (COND ChSetup_DSIn_CK5 CK) (1)) (SETUP DQS (COND ChSetup_DSIn_CK6 CK) (0)) (SETUP DQSNeg (COND ChSetup_DS_CK3 CK) (0.6)) (SETUP DQSNeg (COND ChSetup_DS_CK4 CK) (0.75)) (SETUP DQSNeg (COND ChSetup_DS_CK5 CK) (1)) (SETUP DQSNeg (COND ChSetup_DS_CK6 CK) (0)) (HOLD DQ0 DQS (0.175)) (HOLD DQ1 DQS (0.175)) (HOLD DQ2 DQS (0.175)) (HOLD DQ3 DQS (0.175)) (HOLD DQ4 DQS (0.175)) (HOLD DQ5 DQS (0.175)) (HOLD DQ6 DQS (0.175)) (HOLD DQ7 DQS (0.175)) (HOLD DQ0 DQSNeg (0.175)) (HOLD DQ1 DQSNeg (0.175)) (HOLD DQ2 DQSNeg (0.175)) (HOLD DQ3 DQSNeg (0.175)) (HOLD DQ4 DQSNeg (0.175)) (HOLD DQ5 DQSNeg (0.175)) (HOLD DQ6 DQSNeg (0.175)) (HOLD DQ7 DQSNeg (0.175)) (HOLD RDQS DQS (0.175)) (HOLD RDQS DQSNeg (0.175)) (HOLD ODT CK (0.275)) (HOLD CKE CK (0.275)) (HOLD CSNeg CK (0.275)) (HOLD RASNeg CK (0.275)) (HOLD CASNeg CK (0.275)) (HOLD WENeg CK (0.275)) (HOLD BA0 CK (0.275)) (HOLD BA1 CK (0.275)) (HOLD BA2 CK (0.275)) (HOLD A0 CK (0.275)) (HOLD A1 CK (0.275)) (HOLD A2 CK (0.275)) (HOLD A3 CK (0.275)) (HOLD A4 CK (0.275)) (HOLD A5 CK (0.275)) (HOLD A6 CK (0.275)) (HOLD A7 CK (0.275)) (HOLD A8 CK (0.275)) (HOLD A9 CK (0.275)) (HOLD A10 CK (0.275)) (HOLD A11 CK (0.275)) (HOLD A12 CK (0.275)) (HOLD A13 CK (0.275)) (HOLD DQS (COND ChHold_DSIn_CK3 CK) (1)) (HOLD DQS (COND ChHold_DSIn_CK4 CK) (0.75)) (HOLD DQS (COND ChHold_DSIn_CK5 CK) (0.6)) (HOLD DQS (COND ChHold_DSIn_CK6 CK) (0)) (HOLD DQSNeg (COND ChHold_DS_CK3 CK) (1)) (HOLD DQSNeg (COND ChHold_DS_CK4 CK) (0.75)) (HOLD DQSNeg (COND ChHold_DS_CK5 CK) (0.6)) (HOLD DQSNeg (COND ChHold_DS_CK6 CK) (0)) (WIDTH (COND ChEnable_CK3 CK)(2.4)) (WIDTH (COND ChEnable_CK4 CK)(1.8)) (WIDTH (COND ChEnable_CK5 CK)(1.44)) (WIDTH (COND ChEnable_CK6 CK)(0)) (WIDTH (COND (CL3 == 1) BA0)(3)) (WIDTH (COND (CL3 == 1) BA1)(3)) (WIDTH (COND (CL3 == 1) BA2)(3)) (WIDTH (COND (CL4 == 1) BA0)(2.25)) (WIDTH (COND (CL4 == 1) BA1)(2.25)) (WIDTH (COND (CL4 == 1) BA2)(2.25)) (WIDTH (COND (CL5 == 1) BA0)(1.8)) (WIDTH (COND (CL5 == 1) BA1)(1.8)) (WIDTH (COND (CL5 == 1) BA2)(1.8)) (WIDTH (COND (CL6 == 1) BA0)(0)) (WIDTH (COND (CL6 == 1) BA1)(0)) (WIDTH (COND (CL6 == 1) BA2)(0)) (WIDTH (COND (CL3 == 1) A0)(3)) (WIDTH (COND (CL3 == 1) A1)(3)) (WIDTH (COND (CL3 == 1) A2)(3)) (WIDTH (COND (CL3 == 1) A3)(3)) (WIDTH (COND (CL3 == 1) A4)(3)) (WIDTH (COND (CL3 == 1) A5)(3)) (WIDTH (COND (CL3 == 1) A6)(3)) (WIDTH (COND (CL3 == 1) A7)(3)) (WIDTH (COND (CL3 == 1) A8)(3)) (WIDTH (COND (CL3 == 1) A9)(3)) (WIDTH (COND (CL3 == 1) A10)(3)) (WIDTH (COND (CL3 == 1) A11)(3)) (WIDTH (COND (CL3 == 1) A12)(3)) (WIDTH (COND (CL3 == 1) A13)(3)) (WIDTH (COND (CL4 == 1) A0)(2.25)) (WIDTH (COND (CL4 == 1) A1)(2.25)) (WIDTH (COND (CL4 == 1) A2)(2.25)) (WIDTH (COND (CL4 == 1) A3)(2.25)) (WIDTH (COND (CL4 == 1) A4)(2.25)) (WIDTH (COND (CL4 == 1) A5)(2.25)) (WIDTH (COND (CL4 == 1) A6)(2.25)) (WIDTH (COND (CL4 == 1) A7)(2.25)) (WIDTH (COND (CL4 == 1) A8)(2.25)) (WIDTH (COND (CL4 == 1) A9)(2.25)) (WIDTH (COND (CL4 == 1) A10)(2.25)) (WIDTH (COND (CL4 == 1) A11)(2.25)) (WIDTH (COND (CL4 == 1) A12)(2.25)) (WIDTH (COND (CL4 == 1) A13)(2.25)) (WIDTH (COND (CL5 == 1) A0)(1.8)) (WIDTH (COND (CL5 == 1) A1)(1.8)) (WIDTH (COND (CL5 == 1) A2)(1.8)) (WIDTH (COND (CL5 == 1) A3)(1.8)) (WIDTH (COND (CL5 == 1) A4)(1.8)) (WIDTH (COND (CL5 == 1) A5)(1.8)) (WIDTH (COND (CL5 == 1) A6)(1.8)) (WIDTH (COND (CL5 == 1) A7)(1.8)) (WIDTH (COND (CL5 == 1) A8)(1.8)) (WIDTH (COND (CL5 == 1) A9)(1.8)) (WIDTH (COND (CL5 == 1) A10)(1.8)) (WIDTH (COND (CL5 == 1) A11)(1.8)) (WIDTH (COND (CL5 == 1) A12)(1.8)) (WIDTH (COND (CL5 == 1) A13)(1.8)) (WIDTH (COND (CL6 == 1) A0)(0)) (WIDTH (COND (CL6 == 1) A1)(0)) (WIDTH (COND (CL6 == 1) A2)(0)) (WIDTH (COND (CL6 == 1) A3)(0)) (WIDTH (COND (CL6 == 1) A4)(0)) (WIDTH (COND (CL6 == 1) A5)(0)) (WIDTH (COND (CL6 == 1) A6)(0)) (WIDTH (COND (CL6 == 1) A7)(0)) (WIDTH (COND (CL6 == 1) A8)(0)) (WIDTH (COND (CL6 == 1) A9)(0)) (WIDTH (COND (CL6 == 1) A10)(0)) (WIDTH (COND (CL6 == 1) A11)(0)) (WIDTH (COND (CL6 == 1) A12)(0)) (WIDTH (COND (CL6 == 1) A13)(0)) (WIDTH (COND (CL3 == 1) DQ0)(1.75)) (WIDTH (COND (CL3 == 1) DQ1)(1.75)) (WIDTH (COND (CL3 == 1) DQ2)(1.75)) (WIDTH (COND (CL3 == 1) DQ3)(1.75)) (WIDTH (COND (CL3 == 1) DQ4)(1.75)) (WIDTH (COND (CL3 == 1) DQ5)(1.75)) (WIDTH (COND (CL3 == 1) DQ6)(1.75)) (WIDTH (COND (CL3 == 1) DQ7)(1.75)) (WIDTH (COND (CL4 == 1) DQ0)(1.312)) (WIDTH (COND (CL4 == 1) DQ1)(1.312)) (WIDTH (COND (CL4 == 1) DQ2)(1.312)) (WIDTH (COND (CL4 == 1) DQ3)(1.312)) (WIDTH (COND (CL4 == 1) DQ4)(1.312)) (WIDTH (COND (CL4 == 1) DQ5)(1.312)) (WIDTH (COND (CL4 == 1) DQ6)(1.312)) (WIDTH (COND (CL4 == 1) DQ7)(1.312)) (WIDTH (COND (CL5 == 1) DQ0)(1.05)) (WIDTH (COND (CL5 == 1) DQ1)(1.05)) (WIDTH (COND (CL5 == 1) DQ2)(1.05)) (WIDTH (COND (CL5 == 1) DQ3)(1.05)) (WIDTH (COND (CL5 == 1) DQ4)(1.05)) (WIDTH (COND (CL5 == 1) DQ5)(1.05)) (WIDTH (COND (CL5 == 1) DQ6)(1.05)) (WIDTH (COND (CL5 == 1) DQ7)(1.05)) (WIDTH (COND (CL6 == 1) DQ0)(0)) (WIDTH (COND (CL6 == 1) DQ1)(0)) (WIDTH (COND (CL6 == 1) DQ2)(0)) (WIDTH (COND (CL6 == 1) DQ3)(0)) (WIDTH (COND (CL6 == 1) DQ4)(0)) (WIDTH (COND (CL6 == 1) DQ5)(0)) (WIDTH (COND (CL6 == 1) DQ6)(0)) (WIDTH (COND (CL6 == 1) DQ7)(0)) (WIDTH (COND (DM3 == 1) RDQS)(1.75)) (WIDTH (COND (DM4 == 1) RDQS)(1.312)) (WIDTH (COND (DM5 == 1) RDQS)(1.05)) (WIDTH (COND (DM6 == 1) RDQS)(0)) (WIDTH (COND (CL3 == 1) ODT)(1.75)) (WIDTH (COND (CL4 == 1) ODT)(1.312)) (WIDTH (COND (CL5 == 1) ODT)(1.05)) (WIDTH (COND (CL6 == 1) ODT)(0)) (WIDTH (COND (CL3 == 1) CSNeg)(1.75)) (WIDTH (COND (CL4 == 1) CSNeg)(1.312)) (WIDTH (COND (CL5 == 1) CSNeg)(1.05)) (WIDTH (COND (CL6 == 1) CSNeg)(0)) (WIDTH (COND (CL3 == 1) RASNeg)(1.75)) (WIDTH (COND (CL4 == 1) RASNeg)(1.312)) (WIDTH (COND (CL5 == 1) RASNeg)(1.05)) (WIDTH (COND (CL6 == 1) RASNeg)(0)) (WIDTH (COND (CL3 == 1) CASNeg)(1.75)) (WIDTH (COND (CL4 == 1) CASNeg)(1.312)) (WIDTH (COND (CL5 == 1) CASNeg)(1.05)) (WIDTH (COND (CL6 == 1) CASNeg)(0)) (WIDTH (COND (CL3 == 1) WENeg)(1.75)) (WIDTH (COND (CL4 == 1) WENeg)(1.312)) (WIDTH (COND (CL5 == 1) WENeg)(1.05)) (WIDTH (COND (CL6 == 1) WENeg)(0)) (WIDTH (COND ChNormalCL3 (posedge DQS))(1.75)) (WIDTH (COND ChNormalCL3 (negedge DQS))(1.75)) (WIDTH (COND ChNormalCL4 (posedge DQS))(1.312)) (WIDTH (COND ChNormalCL4 (negedge DQS))(1.312)) (WIDTH (COND ChNormalCL5 (posedge DQS))(1.05)) (WIDTH (COND ChNormalCL5 (negedge DQS))(1.05)) (WIDTH (COND ChNormalCL6 (posedge DQS))(0)) (WIDTH (COND ChNormalCL6 (negedge DQS))(0)) (WIDTH (COND ChPreambleCL3 (negedge DQS))(1.75)) (WIDTH (COND ChPreambleCL4 (negedge DQS))(1.312)) (WIDTH (COND ChPreambleCL5 (negedge DQS))(1.05)) (WIDTH (COND ChPreambleCL6 (negedge DQS))(0)) (WIDTH (COND ChPostambleCL3 (negedge DQS))(2)) (WIDTH (COND ChPostambleCL4 (negedge DQS))(1.5)) (WIDTH (COND ChPostambleCL5 (negedge DQS))(1.2)) (WIDTH (COND ChPostambleCL6 (negedge DQS))(0)) (WIDTH (COND ChDQSNegCL3 (posedge DQSNeg))(1.75)) (WIDTH (COND ChDQSNegCL3 (negedge DQSNeg))(1.75)) (WIDTH (COND ChDQSNegCL4 (posedge DQSNeg))(1.312)) (WIDTH (COND ChDQSNegCL4 (negedge DQSNeg))(1.312)) (WIDTH (COND ChDQSNegCL5 (posedge DQSNeg))(1.05)) (WIDTH (COND ChDQSNegCL5 (negedge DQSNeg))(1.05)) (WIDTH (COND ChDQSNegCL6 (posedge DQSNeg))(0)) (WIDTH (COND ChDQSNegCL6 (negedge DQSNeg))(0)) (WIDTH (COND CheckPreambleCL3 (posedge DQSNeg))(1.75)) (WIDTH (COND CheckPreambleCL4 (posedge DQSNeg))(1.312)) (WIDTH (COND CheckPreambleCL5 (posedge DQSNeg))(1.05)) (WIDTH (COND CheckPreambleCL6 (posedge DQSNeg))(0)) (WIDTH (COND CheckPostambleCL3 (posedge DQSNeg))(2)) (WIDTH (COND CheckPostambleCL4 (posedge DQSNeg))(1.5)) (WIDTH (COND CheckPostambleCL5 (posedge DQSNeg))(1.2)) (WIDTH (COND CheckPostambleCL6 (posedge DQSNeg))(0)) (PERIOD (COND ChEnable_CK3 CK) (5)) (PERIOD (COND ChEnable_CK4 CK) (3.75)) (PERIOD (COND ChEnable_CK5 CK) (3)) (PERIOD (COND ChEnable_CK6 CK) (0)) )) (CELL (CELLTYPE "BUFFER") (INSTANCE dut/BUFSKEW) (DELAY (ABSOLUTE (DEVICE OUT (0.75:0.75:0.75))))) (CELL (CELLTYPE "BUFFER") (INSTANCE %LABEL%/BUFDLL) (DELAY (ABSOLUTE (DEVICE OUT (0.45:0.45:0.45)))) MT47H128M8BT-3EMicron Technology Inc, pdf:09005aef8117c1b1, source:09005aef8117c192 1GbDDR2_2.fm - Rev. H 11/05 EN MT47H128M8BT-3EITMicron Technology Inc, pdf:09005aef8117c1b1, source:09005aef8117c192 1GbDDR2_2.fm - Rev. H 11/05 EN MT47H128M8BT-3ELMicron Technology Inc, pdf:09005aef8117c1b1, source:09005aef8117c192 1GbDDR2_2.fm - Rev. H 11/05 EN MT47H128M8BT-3ELITMicron Technology Inc, pdf:09005aef8117c1b1, source:09005aef8117c192 1GbDDR2_2.fm - Rev. H 11/05 EN The values listed are for VDD = +1.8V ±0.1V (DELAY (ABSOLUTE (IOPATH CK DQ0 (0.45) (0.45) (0.45) (0.45) (0.45) (0.45)) (IOPATH CK DQ1 (0.45) (0.45) (0.45) (0.45) (0.45) (0.45)) (IOPATH CK DQ2 (0.45) (0.45) (0.45) (0.45) (0.45) (0.45)) (IOPATH CK DQ3 (0.45) (0.45) (0.45) (0.45) (0.45) (0.45)) (IOPATH CK DQ4 (0.45) (0.45) (0.45) (0.45) (0.45) (0.45)) (IOPATH CK DQ5 (0.45) (0.45) (0.45) (0.45) (0.45) (0.45)) (IOPATH CK DQ6 (0.45) (0.45) (0.45) (0.45) (0.45) (0.45)) (IOPATH CK DQ7 (0.45) (0.45) (0.45) (0.45) (0.45) (0.45)) (IOPATH CK DQS (0.4) (0.4) (0.4) (0.4) (0.4) (0.4)) (IOPATH CK RDQS (0.4) (0.4) (0.4) (0.4) (0.4) (0.4)) (IOPATH CK DQSNeg (0.4) (0.4) (0.4) (0.4) (0.4) (0.4)) (IOPATH CK RDQSNeg (0.4) (0.4) (0.4) (0.4) (0.4) (0.4)) )) (TIMINGCHECK (SETUP DQ0 DQS (0.1)) (SETUP DQ1 DQS (0.1)) (SETUP DQ2 DQS (0.1)) (SETUP DQ3 DQS (0.1)) (SETUP DQ4 DQS (0.1)) (SETUP DQ5 DQS (0.1)) (SETUP DQ6 DQS (0.1)) (SETUP DQ7 DQS (0.1)) (SETUP DQ0 DQSNeg (0.1)) (SETUP DQ1 DQSNeg (0.1)) (SETUP DQ2 DQSNeg (0.1)) (SETUP DQ3 DQSNeg (0.1)) (SETUP DQ4 DQSNeg (0.1)) (SETUP DQ5 DQSNeg (0.1)) (SETUP DQ6 DQSNeg (0.1)) (SETUP DQ7 DQSNeg (0.1)) (SETUP RDQS DQS (0.1)) (SETUP RDQS DQSNeg (0.1)) (SETUP ODT CK (0.2)) (SETUP CKE CK (0.2)) (SETUP CSNeg CK (0.2)) (SETUP RASNeg CK (0.2)) (SETUP CASNeg CK (0.2)) (SETUP WENeg CK (0.2)) (SETUP BA0 CK (0.2)) (SETUP BA1 CK (0.2)) (SETUP BA2 CK (0.2)) (SETUP A0 CK (0.2)) (SETUP A1 CK (0.2)) (SETUP A2 CK (0.2)) (SETUP A3 CK (0.2)) (SETUP A4 CK (0.2)) (SETUP A5 CK (0.2)) (SETUP A6 CK (0.2)) (SETUP A7 CK (0.2)) (SETUP A8 CK (0.2)) (SETUP A9 CK (0.2)) (SETUP A10 CK (0.2)) (SETUP A11 CK (0.2)) (SETUP A12 CK (0.2)) (SETUP A13 CK (0.2)) (SETUP DQS (COND ChSetup_DSIn_CK3 CK) (0)) (SETUP DQS (COND ChSetup_DSIn_CK4 CK) (0.6)) (SETUP DQS (COND ChSetup_DSIn_CK5 CK) (0.6)) (SETUP DQS (COND ChSetup_DSIn_CK6 CK) (0)) (SETUP DQSNeg (COND ChSetup_DS_CK3 CK) (0)) (SETUP DQSNeg (COND ChSetup_DS_CK4 CK) (0.6)) (SETUP DQSNeg (COND ChSetup_DS_CK5 CK) (0.6)) (SETUP DQSNeg (COND ChSetup_DS_CK6 CK) (0)) (HOLD DQ0 DQS (0.175)) (HOLD DQ1 DQS (0.175)) (HOLD DQ2 DQS (0.175)) (HOLD DQ3 DQS (0.175)) (HOLD DQ4 DQS (0.175)) (HOLD DQ5 DQS (0.175)) (HOLD DQ6 DQS (0.175)) (HOLD DQ7 DQS (0.175)) (HOLD DQ0 DQSNeg (0.175)) (HOLD DQ1 DQSNeg (0.175)) (HOLD DQ2 DQSNeg (0.175)) (HOLD DQ3 DQSNeg (0.175)) (HOLD DQ4 DQSNeg (0.175)) (HOLD DQ5 DQSNeg (0.175)) (HOLD DQ6 DQSNeg (0.175)) (HOLD DQ7 DQSNeg (0.175)) (HOLD RDQS DQS (0.175)) (HOLD RDQS DQSNeg (0.175)) (HOLD ODT CK (0.275)) (HOLD CKE CK (0.275)) (HOLD CSNeg CK (0.275)) (HOLD RASNeg CK (0.275)) (HOLD CASNeg CK (0.275)) (HOLD WENeg CK (0.275)) (HOLD BA0 CK (0.275)) (HOLD BA1 CK (0.275)) (HOLD BA2 CK (0.275)) (HOLD A0 CK (0.275)) (HOLD A1 CK (0.275)) (HOLD A2 CK (0.275)) (HOLD A3 CK (0.275)) (HOLD A4 CK (0.275)) (HOLD A5 CK (0.275)) (HOLD A6 CK (0.275)) (HOLD A7 CK (0.275)) (HOLD A8 CK (0.275)) (HOLD A9 CK (0.275)) (HOLD A10 CK (0.275)) (HOLD A11 CK (0.275)) (HOLD A12 CK (0.275)) (HOLD A13 CK (0.275)) (HOLD DQS (COND ChHold_DSIn_CK3 CK) (0)) (HOLD DQS (COND ChHold_DSIn_CK4 CK) (0.6)) (HOLD DQS (COND ChHold_DSIn_CK5 CK) (0.6)) (HOLD DQS (COND ChHold_DSIn_CK6 CK) (0)) (HOLD DQSNeg (COND ChHold_DS_CK3 CK) (0)) (HOLD DQSNeg (COND ChHold_DS_CK4 CK) (0.6)) (HOLD DQSNeg (COND ChHold_DS_CK5 CK) (0.6)) (HOLD DQSNeg (COND ChHold_DS_CK6 CK) (0)) (WIDTH (COND ChEnable_CK3 CK)(0)) (WIDTH (COND ChEnable_CK4 CK)(1.44)) (WIDTH (COND ChEnable_CK5 CK)(1.44)) (WIDTH (COND ChEnable_CK6 CK)(0)) (WIDTH (COND (CL3 == 1) BA0)(0)) (WIDTH (COND (CL3 == 1) BA1)(0)) (WIDTH (COND (CL3 == 1) BA2)(0)) (WIDTH (COND (CL4 == 1) BA0)(1.8)) (WIDTH (COND (CL4 == 1) BA1)(1.8)) (WIDTH (COND (CL4 == 1) BA2)(1.8)) (WIDTH (COND (CL5 == 1) BA0)(1.8)) (WIDTH (COND (CL5 == 1) BA1)(1.8)) (WIDTH (COND (CL5 == 1) BA2)(1.8)) (WIDTH (COND (CL6 == 1) BA0)(0)) (WIDTH (COND (CL6 == 1) BA1)(0)) (WIDTH (COND (CL6 == 1) BA2)(0)) (WIDTH (COND (CL3 == 1) A0)(0)) (WIDTH (COND (CL3 == 1) A1)(0)) (WIDTH (COND (CL3 == 1) A2)(0)) (WIDTH (COND (CL3 == 1) A3)(0)) (WIDTH (COND (CL3 == 1) A4)(0)) (WIDTH (COND (CL3 == 1) A5)(0)) (WIDTH (COND (CL3 == 1) A6)(0)) (WIDTH (COND (CL3 == 1) A7)(0)) (WIDTH (COND (CL3 == 1) A8)(0)) (WIDTH (COND (CL3 == 1) A9)(0)) (WIDTH (COND (CL3 == 1) A10)(0)) (WIDTH (COND (CL3 == 1) A11)(0)) (WIDTH (COND (CL3 == 1) A12)(0)) (WIDTH (COND (CL3 == 1) A13)(0)) (WIDTH (COND (CL4 == 1) A0)(1.8)) (WIDTH (COND (CL4 == 1) A1)(1.8)) (WIDTH (COND (CL4 == 1) A2)(1.8)) (WIDTH (COND (CL4 == 1) A3)(1.8)) (WIDTH (COND (CL4 == 1) A4)(1.8)) (WIDTH (COND (CL4 == 1) A5)(1.8)) (WIDTH (COND (CL4 == 1) A6)(1.8)) (WIDTH (COND (CL4 == 1) A7)(1.8)) (WIDTH (COND (CL4 == 1) A8)(1.8)) (WIDTH (COND (CL4 == 1) A9)(1.8)) (WIDTH (COND (CL4 == 1) A10)(1.8)) (WIDTH (COND (CL4 == 1) A11)(1.8)) (WIDTH (COND (CL4 == 1) A12)(1.8)) (WIDTH (COND (CL4 == 1) A13)(1.8)) (WIDTH (COND (CL5 == 1) A0)(1.8)) (WIDTH (COND (CL5 == 1) A1)(1.8)) (WIDTH (COND (CL5 == 1) A2)(1.8)) (WIDTH (COND (CL5 == 1) A3)(1.8)) (WIDTH (COND (CL5 == 1) A4)(1.8)) (WIDTH (COND (CL5 == 1) A5)(1.8)) (WIDTH (COND (CL5 == 1) A6)(1.8)) (WIDTH (COND (CL5 == 1) A7)(1.8)) (WIDTH (COND (CL5 == 1) A8)(1.8)) (WIDTH (COND (CL5 == 1) A9)(1.8)) (WIDTH (COND (CL5 == 1) A10)(1.8)) (WIDTH (COND (CL5 == 1) A11)(1.8)) (WIDTH (COND (CL5 == 1) A12)(1.8)) (WIDTH (COND (CL5 == 1) A13)(1.8)) (WIDTH (COND (CL6 == 1) A0)(0)) (WIDTH (COND (CL6 == 1) A1)(0)) (WIDTH (COND (CL6 == 1) A2)(0)) (WIDTH (COND (CL6 == 1) A3)(0)) (WIDTH (COND (CL6 == 1) A4)(0)) (WIDTH (COND (CL6 == 1) A5)(0)) (WIDTH (COND (CL6 == 1) A6)(0)) (WIDTH (COND (CL6 == 1) A7)(0)) (WIDTH (COND (CL6 == 1) A8)(0)) (WIDTH (COND (CL6 == 1) A9)(0)) (WIDTH (COND (CL6 == 1) A10)(0)) (WIDTH (COND (CL6 == 1) A11)(0)) (WIDTH (COND (CL6 == 1) A12)(0)) (WIDTH (COND (CL6 == 1) A13)(0)) (WIDTH (COND (CL3 == 1) DQ0)(0)) (WIDTH (COND (CL3 == 1) DQ1)(0)) (WIDTH (COND (CL3 == 1) DQ2)(0)) (WIDTH (COND (CL3 == 1) DQ3)(0)) (WIDTH (COND (CL3 == 1) DQ4)(0)) (WIDTH (COND (CL3 == 1) DQ5)(0)) (WIDTH (COND (CL3 == 1) DQ6)(0)) (WIDTH (COND (CL3 == 1) DQ7)(0)) (WIDTH (COND (CL4 == 1) DQ0)(1.05)) (WIDTH (COND (CL4 == 1) DQ1)(1.05)) (WIDTH (COND (CL4 == 1) DQ2)(1.05)) (WIDTH (COND (CL4 == 1) DQ3)(1.05)) (WIDTH (COND (CL4 == 1) DQ4)(1.05)) (WIDTH (COND (CL4 == 1) DQ5)(1.05)) (WIDTH (COND (CL4 == 1) DQ6)(1.05)) (WIDTH (COND (CL4 == 1) DQ7)(1.05)) (WIDTH (COND (CL5 == 1) DQ0)(1.05)) (WIDTH (COND (CL5 == 1) DQ1)(1.05)) (WIDTH (COND (CL5 == 1) DQ2)(1.05)) (WIDTH (COND (CL5 == 1) DQ3)(1.05)) (WIDTH (COND (CL5 == 1) DQ4)(1.05)) (WIDTH (COND (CL5 == 1) DQ5)(1.05)) (WIDTH (COND (CL5 == 1) DQ6)(1.05)) (WIDTH (COND (CL5 == 1) DQ7)(1.05)) (WIDTH (COND (CL6 == 1) DQ0)(0)) (WIDTH (COND (CL6 == 1) DQ1)(0)) (WIDTH (COND (CL6 == 1) DQ2)(0)) (WIDTH (COND (CL6 == 1) DQ3)(0)) (WIDTH (COND (CL6 == 1) DQ4)(0)) (WIDTH (COND (CL6 == 1) DQ5)(0)) (WIDTH (COND (CL6 == 1) DQ6)(0)) (WIDTH (COND (CL6 == 1) DQ7)(0)) (WIDTH (COND (DM3 == 1) RDQS)(0)) (WIDTH (COND (DM4 == 1) RDQS)(1.05)) (WIDTH (COND (DM5 == 1) RDQS)(1.05)) (WIDTH (COND (DM6 == 1) RDQS)(0)) (WIDTH (COND (CL3 == 1) ODT)(0)) (WIDTH (COND (CL4 == 1) ODT)(1.05)) (WIDTH (COND (CL5 == 1) ODT)(1.05)) (WIDTH (COND (CL6 == 1) ODT)(0)) (WIDTH (COND (CL3 == 1) CSNeg)(0)) (WIDTH (COND (CL4 == 1) CSNeg)(1.05)) (WIDTH (COND (CL5 == 1) CSNeg)(1.05)) (WIDTH (COND (CL6 == 1) CSNeg)(0)) (WIDTH (COND (CL3 == 1) RASNeg)(0)) (WIDTH (COND (CL4 == 1) RASNeg)(1.05)) (WIDTH (COND (CL5 == 1) RASNeg)(1.05)) (WIDTH (COND (CL6 == 1) RASNeg)(0)) (WIDTH (COND (CL3 == 1) CASNeg)(0)) (WIDTH (COND (CL4 == 1) CASNeg)(1.05)) (WIDTH (COND (CL5 == 1) CASNeg)(1.05)) (WIDTH (COND (CL6 == 1) CASNeg)(0)) (WIDTH (COND (CL3 == 1) WENeg)(0)) (WIDTH (COND (CL4 == 1) WENeg)(1.05)) (WIDTH (COND (CL5 == 1) WENeg)(1.05)) (WIDTH (COND (CL6 == 1) WENeg)(0)) (WIDTH (COND ChNormalCL3 (posedge DQS))(0)) (WIDTH (COND ChNormalCL3 (negedge DQS))(0)) (WIDTH (COND ChNormalCL4 (posedge DQS))(1.05)) (WIDTH (COND ChNormalCL4 (negedge DQS))(1.05)) (WIDTH (COND ChNormalCL5 (posedge DQS))(1.05)) (WIDTH (COND ChNormalCL5 (negedge DQS))(1.05)) (WIDTH (COND ChNormalCL6 (posedge DQS))(0)) (WIDTH (COND ChNormalCL6 (negedge DQS))(0)) (WIDTH (COND ChPreambleCL3 (negedge DQS))(0)) (WIDTH (COND ChPreambleCL4 (negedge DQS))(1.05)) (WIDTH (COND ChPreambleCL5 (negedge DQS))(1.05)) (WIDTH (COND ChPreambleCL6 (negedge DQS))(0)) (WIDTH (COND ChPostambleCL3 (negedge DQS))(0)) (WIDTH (COND ChPostambleCL4 (negedge DQS))(1.2)) (WIDTH (COND ChPostambleCL5 (negedge DQS))(1.2)) (WIDTH (COND ChPostambleCL6 (negedge DQS))(0)) (WIDTH (COND ChDQSNegCL3 (posedge DQSNeg))(0)) (WIDTH (COND ChDQSNegCL3 (negedge DQSNeg))(0)) (WIDTH (COND ChDQSNegCL4 (posedge DQSNeg))(1.05)) (WIDTH (COND ChDQSNegCL4 (negedge DQSNeg))(1.05)) (WIDTH (COND ChDQSNegCL5 (posedge DQSNeg))(1.05)) (WIDTH (COND ChDQSNegCL5 (negedge DQSNeg))(1.05)) (WIDTH (COND ChDQSNegCL6 (posedge DQSNeg))(0)) (WIDTH (COND ChDQSNegCL6 (negedge DQSNeg))(0)) (WIDTH (COND CheckPreambleCL3 (posedge DQSNeg))(0)) (WIDTH (COND CheckPreambleCL4 (posedge DQSNeg))(1.05)) (WIDTH (COND CheckPreambleCL5 (posedge DQSNeg))(1.05)) (WIDTH (COND CheckPreambleCL6 (posedge DQSNeg))(0)) (WIDTH (COND CheckPostambleCL3 (posedge DQSNeg))(0)) (WIDTH (COND CheckPostambleCL4 (posedge DQSNeg))(1.2)) (WIDTH (COND CheckPostambleCL5 (posedge DQSNeg))(1.2)) (WIDTH (COND CheckPostambleCL6 (posedge DQSNeg))(0)) (PERIOD (COND ChEnable_CK3 CK) (0)) (PERIOD (COND ChEnable_CK4 CK) (3)) (PERIOD (COND ChEnable_CK5 CK) (3)) (PERIOD (COND ChEnable_CK6 CK) (0)) )) (CELL (CELLTYPE "BUFFER") (INSTANCE dut/BUFSKEW) (DELAY (ABSOLUTE (DEVICE OUT (0.75:0.75:0.75))))) (CELL (CELLTYPE "BUFFER") (INSTANCE %LABEL%/BUFDLL) (DELAY (ABSOLUTE (DEVICE OUT (0.45:0.45:0.45)))) MT47H128M8BT-37EMicron Technology Inc, pdf:09005aef8117c1b1, source:09005aef8117c192 1GbDDR2_2.fm - Rev. H 11/05 EN MT47H128M8BT-37EITMicron Technology Inc, pdf:09005aef8117c1b1, source:09005aef8117c192 1GbDDR2_2.fm - Rev. H 11/05 EN MT47H128M8BT-37ELMicron Technology Inc, pdf:09005aef8117c1b1, source:09005aef8117c192 1GbDDR2_2.fm - Rev. H 11/05 EN MT47H128M8BT-37ELITMicron Technology Inc, pdf:09005aef8117c1b1, source:09005aef8117c192 1GbDDR2_2.fm - Rev. H 11/05 EN The values listed are for VDD = +1.8V ±0.1V (DELAY (ABSOLUTE (IOPATH CK DQ0 (0.5) (0.5) (0.5) (0.5) (0.5) (0.5)) (IOPATH CK DQ1 (0.5) (0.5) (0.5) (0.5) (0.5) (0.5)) (IOPATH CK DQ2 (0.5) (0.5) (0.5) (0.5) (0.5) (0.5)) (IOPATH CK DQ3 (0.5) (0.5) (0.5) (0.5) (0.5) (0.5)) (IOPATH CK DQ4 (0.5) (0.5) (0.5) (0.5) (0.5) (0.5)) (IOPATH CK DQ5 (0.5) (0.5) (0.5) (0.5) (0.5) (0.5)) (IOPATH CK DQ6 (0.5) (0.5) (0.5) (0.5) (0.5) (0.5)) (IOPATH CK DQ7 (0.5) (0.5) (0.5) (0.5) (0.5) (0.5)) (IOPATH CK DQS (0.45) (0.45) (0.45) (0.45) (0.45) (0.45)) (IOPATH CK RDQS (0.45) (0.45) (0.45) (0.45) (0.45) (0.45)) (IOPATH CK DQSNeg (0.45) (0.45) (0.45) (0.45) (0.45) (0.45)) (IOPATH CK RDQSNeg (0.45) (0.45) (0.45) (0.45) (0.45) (0.45)) )) (TIMINGCHECK (SETUP DQ0 DQS (0.1)) (SETUP DQ1 DQS (0.1)) (SETUP DQ2 DQS (0.1)) (SETUP DQ3 DQS (0.1)) (SETUP DQ4 DQS (0.1)) (SETUP DQ5 DQS (0.1)) (SETUP DQ6 DQS (0.1)) (SETUP DQ7 DQS (0.1)) (SETUP DQ0 DQSNeg (0.1)) (SETUP DQ1 DQSNeg (0.1)) (SETUP DQ2 DQSNeg (0.1)) (SETUP DQ3 DQSNeg (0.1)) (SETUP DQ4 DQSNeg (0.1)) (SETUP DQ5 DQSNeg (0.1)) (SETUP DQ6 DQSNeg (0.1)) (SETUP DQ7 DQSNeg (0.1)) (SETUP RDQS DQS (0.1)) (SETUP RDQS DQSNeg (0.1)) (SETUP ODT CK (0.25)) (SETUP CKE CK (0.25)) (SETUP CSNeg CK (0.25)) (SETUP RASNeg CK (0.25)) (SETUP CASNeg CK (0.25)) (SETUP WENeg CK (0.25)) (SETUP BA0 CK (0.25)) (SETUP BA1 CK (0.25)) (SETUP BA2 CK (0.25)) (SETUP A0 CK (0.25)) (SETUP A1 CK (0.25)) (SETUP A2 CK (0.25)) (SETUP A3 CK (0.25)) (SETUP A4 CK (0.25)) (SETUP A5 CK (0.25)) (SETUP A6 CK (0.25)) (SETUP A7 CK (0.25)) (SETUP A8 CK (0.25)) (SETUP A9 CK (0.25)) (SETUP A10 CK (0.25)) (SETUP A11 CK (0.25)) (SETUP A12 CK (0.25)) (SETUP A13 CK (0.25)) (SETUP DQS (COND ChSetup_DSIn_CK3 CK) (1)) (SETUP DQS (COND ChSetup_DSIn_CK4 CK) (0.75)) (SETUP DQS (COND ChSetup_DSIn_CK5 CK) (0)) (SETUP DQS (COND ChSetup_DSIn_CK6 CK) (0)) (SETUP DQSNeg (COND ChSetup_DS_CK3 CK) (1)) (SETUP DQSNeg (COND ChSetup_DS_CK4 CK) (0.75)) (SETUP DQSNeg (COND ChSetup_DS_CK5 CK) (0)) (SETUP DQSNeg (COND ChSetup_DS_CK6 CK) (0)) (HOLD DQ0 DQS (0.225)) (HOLD DQ1 DQS (0.225)) (HOLD DQ2 DQS (0.225)) (HOLD DQ3 DQS (0.225)) (HOLD DQ4 DQS (0.225)) (HOLD DQ5 DQS (0.225)) (HOLD DQ6 DQS (0.225)) (HOLD DQ7 DQS (0.225)) (HOLD DQ0 DQSNeg (0.225)) (HOLD DQ1 DQSNeg (0.225)) (HOLD DQ2 DQSNeg (0.225)) (HOLD DQ3 DQSNeg (0.225)) (HOLD DQ4 DQSNeg (0.225)) (HOLD DQ5 DQSNeg (0.225)) (HOLD DQ6 DQSNeg (0.225)) (HOLD DQ7 DQSNeg (0.225)) (HOLD RDQS DQS (0.225)) (HOLD RDQS DQSNeg (0.225)) (HOLD ODT CK (0.375)) (HOLD CKE CK (0.375)) (HOLD CSNeg CK (0.375)) (HOLD RASNeg CK (0.375)) (HOLD CASNeg CK (0.375)) (HOLD WENeg CK (0.375)) (HOLD BA0 CK (0.375)) (HOLD BA1 CK (0.375)) (HOLD BA2 CK (0.375)) (HOLD A0 CK (0.375)) (HOLD A1 CK (0.375)) (HOLD A2 CK (0.375)) (HOLD A3 CK (0.375)) (HOLD A4 CK (0.375)) (HOLD A5 CK (0.375)) (HOLD A6 CK (0.375)) (HOLD A7 CK (0.375)) (HOLD A8 CK (0.375)) (HOLD A9 CK (0.375)) (HOLD A10 CK (0.375)) (HOLD A11 CK (0.375)) (HOLD A12 CK (0.375)) (HOLD A13 CK (0.375)) (HOLD DQS (COND ChHold_DSIn_CK3 CK) (1)) (HOLD DQS (COND ChHold_DSIn_CK4 CK) (0.75)) (HOLD DQS (COND ChHold_DSIn_CK5 CK) (0)) (HOLD DQS (COND ChHold_DSIn_CK6 CK) (0)) (HOLD DQSNeg (COND ChHold_DS_CK3 CK) (1)) (HOLD DQSNeg (COND ChHold_DS_CK4 CK) (0.75)) (HOLD DQSNeg (COND ChHold_DS_CK5 CK) (0)) (HOLD DQSNeg (COND ChHold_DS_CK6 CK) (0)) (WIDTH (COND ChEnable_CK3 CK)(2.4)) (WIDTH (COND ChEnable_CK4 CK)(1.8)) (WIDTH (COND ChEnable_CK5 CK)(0)) (WIDTH (COND ChEnable_CK6 CK)(0)) (WIDTH (COND (CL3 == 1) BA0)(3)) (WIDTH (COND (CL3 == 1) BA1)(3)) (WIDTH (COND (CL3 == 1) BA2)(3)) (WIDTH (COND (CL4 == 1) BA0)(2.25)) (WIDTH (COND (CL4 == 1) BA1)(2.25)) (WIDTH (COND (CL4 == 1) BA2)(2.25)) (WIDTH (COND (CL5 == 1) BA0)(0)) (WIDTH (COND (CL5 == 1) BA1)(0)) (WIDTH (COND (CL5 == 1) BA2)(0)) (WIDTH (COND (CL6 == 1) BA0)(0)) (WIDTH (COND (CL6 == 1) BA1)(0)) (WIDTH (COND (CL6 == 1) BA2)(0)) (WIDTH (COND (CL3 == 1) A0)(3)) (WIDTH (COND (CL3 == 1) A1)(3)) (WIDTH (COND (CL3 == 1) A2)(3)) (WIDTH (COND (CL3 == 1) A3)(3)) (WIDTH (COND (CL3 == 1) A4)(3)) (WIDTH (COND (CL3 == 1) A5)(3)) (WIDTH (COND (CL3 == 1) A6)(3)) (WIDTH (COND (CL3 == 1) A7)(3)) (WIDTH (COND (CL3 == 1) A8)(3)) (WIDTH (COND (CL3 == 1) A9)(3)) (WIDTH (COND (CL3 == 1) A10)(3)) (WIDTH (COND (CL3 == 1) A11)(3)) (WIDTH (COND (CL3 == 1) A12)(3)) (WIDTH (COND (CL3 == 1) A13)(3)) (WIDTH (COND (CL4 == 1) A0)(2.25)) (WIDTH (COND (CL4 == 1) A1)(2.25)) (WIDTH (COND (CL4 == 1) A2)(2.25)) (WIDTH (COND (CL4 == 1) A3)(2.25)) (WIDTH (COND (CL4 == 1) A4)(2.25)) (WIDTH (COND (CL4 == 1) A5)(2.25)) (WIDTH (COND (CL4 == 1) A6)(2.25)) (WIDTH (COND (CL4 == 1) A7)(2.25)) (WIDTH (COND (CL4 == 1) A8)(2.25)) (WIDTH (COND (CL4 == 1) A9)(2.25)) (WIDTH (COND (CL4 == 1) A10)(2.25)) (WIDTH (COND (CL4 == 1) A11)(2.25)) (WIDTH (COND (CL4 == 1) A12)(2.25)) (WIDTH (COND (CL4 == 1) A13)(2.25)) (WIDTH (COND (CL5 == 1) A0)(0)) (WIDTH (COND (CL5 == 1) A1)(0)) (WIDTH (COND (CL5 == 1) A2)(0)) (WIDTH (COND (CL5 == 1) A3)(0)) (WIDTH (COND (CL5 == 1) A4)(0)) (WIDTH (COND (CL5 == 1) A5)(0)) (WIDTH (COND (CL5 == 1) A6)(0)) (WIDTH (COND (CL5 == 1) A7)(0)) (WIDTH (COND (CL5 == 1) A8)(0)) (WIDTH (COND (CL5 == 1) A9)(0)) (WIDTH (COND (CL5 == 1) A10)(0)) (WIDTH (COND (CL5 == 1) A11)(0)) (WIDTH (COND (CL5 == 1) A12)(0)) (WIDTH (COND (CL5 == 1) A13)(0)) (WIDTH (COND (CL6 == 1) A0)(0)) (WIDTH (COND (CL6 == 1) A1)(0)) (WIDTH (COND (CL6 == 1) A2)(0)) (WIDTH (COND (CL6 == 1) A3)(0)) (WIDTH (COND (CL6 == 1) A4)(0)) (WIDTH (COND (CL6 == 1) A5)(0)) (WIDTH (COND (CL6 == 1) A6)(0)) (WIDTH (COND (CL6 == 1) A7)(0)) (WIDTH (COND (CL6 == 1) A8)(0)) (WIDTH (COND (CL6 == 1) A9)(0)) (WIDTH (COND (CL6 == 1) A10)(0)) (WIDTH (COND (CL6 == 1) A11)(0)) (WIDTH (COND (CL6 == 1) A12)(0)) (WIDTH (COND (CL6 == 1) A13)(0)) (WIDTH (COND (CL3 == 1) DQ0)(1.75)) (WIDTH (COND (CL3 == 1) DQ1)(1.75)) (WIDTH (COND (CL3 == 1) DQ2)(1.75)) (WIDTH (COND (CL3 == 1) DQ3)(1.75)) (WIDTH (COND (CL3 == 1) DQ4)(1.75)) (WIDTH (COND (CL3 == 1) DQ5)(1.75)) (WIDTH (COND (CL3 == 1) DQ6)(1.75)) (WIDTH (COND (CL3 == 1) DQ7)(1.75)) (WIDTH (COND (CL4 == 1) DQ0)(1.312)) (WIDTH (COND (CL4 == 1) DQ1)(1.312)) (WIDTH (COND (CL4 == 1) DQ2)(1.312)) (WIDTH (COND (CL4 == 1) DQ3)(1.312)) (WIDTH (COND (CL4 == 1) DQ4)(1.312)) (WIDTH (COND (CL4 == 1) DQ5)(1.312)) (WIDTH (COND (CL4 == 1) DQ6)(1.312)) (WIDTH (COND (CL4 == 1) DQ7)(1.312)) (WIDTH (COND (CL5 == 1) DQ0)(0)) (WIDTH (COND (CL5 == 1) DQ1)(0)) (WIDTH (COND (CL5 == 1) DQ2)(0)) (WIDTH (COND (CL5 == 1) DQ3)(0)) (WIDTH (COND (CL5 == 1) DQ4)(0)) (WIDTH (COND (CL5 == 1) DQ5)(0)) (WIDTH (COND (CL5 == 1) DQ6)(0)) (WIDTH (COND (CL5 == 1) DQ7)(0)) (WIDTH (COND (CL6 == 1) DQ0)(0)) (WIDTH (COND (CL6 == 1) DQ1)(0)) (WIDTH (COND (CL6 == 1) DQ2)(0)) (WIDTH (COND (CL6 == 1) DQ3)(0)) (WIDTH (COND (CL6 == 1) DQ4)(0)) (WIDTH (COND (CL6 == 1) DQ5)(0)) (WIDTH (COND (CL6 == 1) DQ6)(0)) (WIDTH (COND (CL6 == 1) DQ7)(0)) (WIDTH (COND (DM3 == 1) RDQS)(1.75)) (WIDTH (COND (DM4 == 1) RDQS)(1.312)) (WIDTH (COND (DM5 == 1) RDQS)(0)) (WIDTH (COND (DM6 == 1) RDQS)(0)) (WIDTH (COND (CL3 == 1) ODT)(1.75)) (WIDTH (COND (CL4 == 1) ODT)(1.312)) (WIDTH (COND (CL5 == 1) ODT)(0)) (WIDTH (COND (CL6 == 1) ODT)(0)) (WIDTH (COND (CL3 == 1) CSNeg)(1.75)) (WIDTH (COND (CL4 == 1) CSNeg)(1.312)) (WIDTH (COND (CL5 == 1) CSNeg)(0)) (WIDTH (COND (CL6 == 1) CSNeg)(0)) (WIDTH (COND (CL3 == 1) RASNeg)(1.75)) (WIDTH (COND (CL4 == 1) RASNeg)(1.312)) (WIDTH (COND (CL5 == 1) RASNeg)(0)) (WIDTH (COND (CL6 == 1) RASNeg)(0)) (WIDTH (COND (CL3 == 1) CASNeg)(1.75)) (WIDTH (COND (CL4 == 1) CASNeg)(1.312)) (WIDTH (COND (CL5 == 1) CASNeg)(0)) (WIDTH (COND (CL6 == 1) CASNeg)(0)) (WIDTH (COND (CL3 == 1) WENeg)(1.75)) (WIDTH (COND (CL4 == 1) WENeg)(1.312)) (WIDTH (COND (CL5 == 1) WENeg)(0)) (WIDTH (COND (CL6 == 1) WENeg)(0)) (WIDTH (COND ChNormalCL3 (posedge DQS))(1.75)) (WIDTH (COND ChNormalCL3 (negedge DQS))(1.75)) (WIDTH (COND ChNormalCL4 (posedge DQS))(1.312)) (WIDTH (COND ChNormalCL4 (negedge DQS))(1.312)) (WIDTH (COND ChNormalCL5 (posedge DQS))(0)) (WIDTH (COND ChNormalCL5 (negedge DQS))(0)) (WIDTH (COND ChNormalCL6 (posedge DQS))(0)) (WIDTH (COND ChNormalCL6 (negedge DQS))(0)) (WIDTH (COND ChPreambleCL3 (negedge DQS))(1.25)) (WIDTH (COND ChPreambleCL4 (negedge DQS))(0.937)) (WIDTH (COND ChPreambleCL5 (negedge DQS))(0)) (WIDTH (COND ChPreambleCL6 (negedge DQS))(0)) (WIDTH (COND ChPostambleCL3 (negedge DQS))(2)) (WIDTH (COND ChPostambleCL4 (negedge DQS))(1.5)) (WIDTH (COND ChPostambleCL5 (negedge DQS))(0)) (WIDTH (COND ChPostambleCL6 (negedge DQS))(0)) (WIDTH (COND ChDQSNegCL3 (posedge DQSNeg))(1.75)) (WIDTH (COND ChDQSNegCL3 (negedge DQSNeg))(1.75)) (WIDTH (COND ChDQSNegCL4 (posedge DQSNeg))(1.312)) (WIDTH (COND ChDQSNegCL4 (negedge DQSNeg))(1.312)) (WIDTH (COND ChDQSNegCL5 (posedge DQSNeg))(0)) (WIDTH (COND ChDQSNegCL5 (negedge DQSNeg))(0)) (WIDTH (COND ChDQSNegCL6 (posedge DQSNeg))(0)) (WIDTH (COND ChDQSNegCL6 (negedge DQSNeg))(0)) (WIDTH (COND CheckPreambleCL3 (posedge DQSNeg))(1.25)) (WIDTH (COND CheckPreambleCL4 (posedge DQSNeg))(0.937)) (WIDTH (COND CheckPreambleCL5 (posedge DQSNeg))(0)) (WIDTH (COND CheckPreambleCL6 (posedge DQSNeg))(0)) (WIDTH (COND CheckPostambleCL3 (posedge DQSNeg))(2)) (WIDTH (COND CheckPostambleCL4 (posedge DQSNeg))(1.5)) (WIDTH (COND CheckPostambleCL5 (posedge DQSNeg))(0)) (WIDTH (COND CheckPostambleCL6 (posedge DQSNeg))(0)) (PERIOD (COND ChEnable_CK3 CK) (5)) (PERIOD (COND ChEnable_CK4 CK) (3.75)) (PERIOD (COND ChEnable_CK5 CK) (0)) (PERIOD (COND ChEnable_CK6 CK) (0)) )) (CELL (CELLTYPE "BUFFER") (INSTANCE dut/BUFSKEW) (DELAY (ABSOLUTE (DEVICE OUT (0.937:0.937:0.937))))) (CELL (CELLTYPE "BUFFER") (INSTANCE %LABEL%/BUFDLL) (DELAY (ABSOLUTE (DEVICE OUT (0.5:0.5:0.5)))) MT47H128M8BT-5EMicron Technology Inc, pdf:09005aef8117c1b1, source:09005aef8117c192 1GbDDR2_2.fm - Rev. H 11/05 EN MT47H128M8BT-5EITMicron Technology Inc, pdf:09005aef8117c1b1, source:09005aef8117c192 1GbDDR2_2.fm - Rev. H 11/05 EN MT47H128M8BT-5ELMicron Technology Inc, pdf:09005aef8117c1b1, source:09005aef8117c192 1GbDDR2_2.fm - Rev. H 11/05 EN MT47H128M8BT-5ELITMicron Technology Inc, pdf:09005aef8117c1b1, source:09005aef8117c192 1GbDDR2_2.fm - Rev. H 11/05 EN The values listed are for VDD = +1.8V ±0.1V (DELAY (ABSOLUTE (IOPATH CK DQ0 (0.6) (0.6) (0.6) (0.6) (0.6) (0.6)) (IOPATH CK DQ1 (0.6) (0.6) (0.6) (0.6) (0.6) (0.6)) (IOPATH CK DQ2 (0.6) (0.6) (0.6) (0.6) (0.6) (0.6)) (IOPATH CK DQ3 (0.6) (0.6) (0.6) (0.6) (0.6) (0.6)) (IOPATH CK DQ4 (0.6) (0.6) (0.6) (0.6) (0.6) (0.6)) (IOPATH CK DQ5 (0.6) (0.6) (0.6) (0.6) (0.6) (0.6)) (IOPATH CK DQ6 (0.6) (0.6) (0.6) (0.6) (0.6) (0.6)) (IOPATH CK DQ7 (0.6) (0.6) (0.6) (0.6) (0.6) (0.6)) (IOPATH CK DQS (0.5) (0.5) (0.5) (0.5) (0.5) (0.5)) (IOPATH CK RDQS (0.5) (0.5) (0.5) (0.5) (0.5) (0.5)) (IOPATH CK DQSNeg (0.5) (0.5) (0.5) (0.5) (0.5) (0.5)) (IOPATH CK RDQSNeg (0.5) (0.5) (0.5) (0.5) (0.5) (0.5)) )) (TIMINGCHECK (SETUP DQ0 DQS (0.15)) (SETUP DQ1 DQS (0.15)) (SETUP DQ2 DQS (0.15)) (SETUP DQ3 DQS (0.15)) (SETUP DQ4 DQS (0.15)) (SETUP DQ5 DQS (0.15)) (SETUP DQ6 DQS (0.15)) (SETUP DQ7 DQS (0.15)) (SETUP DQ0 DQSNeg (0.15)) (SETUP DQ1 DQSNeg (0.15)) (SETUP DQ2 DQSNeg (0.15)) (SETUP DQ3 DQSNeg (0.15)) (SETUP DQ4 DQSNeg (0.15)) (SETUP DQ5 DQSNeg (0.15)) (SETUP DQ6 DQSNeg (0.15)) (SETUP DQ7 DQSNeg (0.15)) (SETUP RDQS DQS (0.15)) (SETUP RDQS DQSNeg (0.15)) (SETUP ODT CK (0.35)) (SETUP CKE CK (0.35)) (SETUP CSNeg CK (0.35)) (SETUP RASNeg CK (0.35)) (SETUP CASNeg CK (0.35)) (SETUP WENeg CK (0.35)) (SETUP BA0 CK (0.35)) (SETUP BA1 CK (0.35)) (SETUP BA2 CK (0.35)) (SETUP A0 CK (0.35)) (SETUP A1 CK (0.35)) (SETUP A2 CK (0.35)) (SETUP A3 CK (0.35)) (SETUP A4 CK (0.35)) (SETUP A5 CK (0.35)) (SETUP A6 CK (0.35)) (SETUP A7 CK (0.35)) (SETUP A8 CK (0.35)) (SETUP A9 CK (0.35)) (SETUP A10 CK (0.35)) (SETUP A11 CK (0.35)) (SETUP A12 CK (0.35)) (SETUP A13 CK (0.35)) (SETUP DQS (COND ChSetup_DSIn_CK3 CK) (1)) (SETUP DQS (COND ChSetup_DSIn_CK4 CK) (1)) (SETUP DQS (COND ChSetup_DSIn_CK5 CK) (0)) (SETUP DQS (COND ChSetup_DSIn_CK6 CK) (0)) (SETUP DQSNeg (COND ChSetup_DS_CK3 CK) (1)) (SETUP DQSNeg (COND ChSetup_DS_CK4 CK) (1)) (SETUP DQSNeg (COND ChSetup_DS_CK5 CK) (0)) (SETUP DQSNeg (COND ChSetup_DS_CK6 CK) (0)) (HOLD DQ0 DQS (0.275)) (HOLD DQ1 DQS (0.275)) (HOLD DQ2 DQS (0.275)) (HOLD DQ3 DQS (0.275)) (HOLD DQ4 DQS (0.275)) (HOLD DQ5 DQS (0.275)) (HOLD DQ6 DQS (0.275)) (HOLD DQ7 DQS (0.275)) (HOLD DQ0 DQSNeg (0.275)) (HOLD DQ1 DQSNeg (0.275)) (HOLD DQ2 DQSNeg (0.275)) (HOLD DQ3 DQSNeg (0.275)) (HOLD DQ4 DQSNeg (0.275)) (HOLD DQ5 DQSNeg (0.275)) (HOLD DQ6 DQSNeg (0.275)) (HOLD DQ7 DQSNeg (0.275)) (HOLD RDQS DQS (0.275)) (HOLD RDQS DQSNeg (0.275)) (HOLD ODT CK (0.475)) (HOLD CKE CK (0.475)) (HOLD CSNeg CK (0.475)) (HOLD RASNeg CK (0.475)) (HOLD CASNeg CK (0.475)) (HOLD WENeg CK (0.475)) (HOLD BA0 CK (0.475)) (HOLD BA1 CK (0.475)) (HOLD BA2 CK (0.475)) (HOLD A0 CK (0.475)) (HOLD A1 CK (0.475)) (HOLD A2 CK (0.475)) (HOLD A3 CK (0.475)) (HOLD A4 CK (0.475)) (HOLD A5 CK (0.475)) (HOLD A6 CK (0.475)) (HOLD A7 CK (0.475)) (HOLD A8 CK (0.475)) (HOLD A9 CK (0.475)) (HOLD A10 CK (0.475)) (HOLD A11 CK (0.475)) (HOLD A12 CK (0.475)) (HOLD A13 CK (0.475)) (HOLD DQS (COND ChHold_DSIn_CK3 CK) (1)) (HOLD DQS (COND ChHold_DSIn_CK4 CK) (1)) (HOLD DQS (COND ChHold_DSIn_CK5 CK) (0)) (HOLD DQS (COND ChHold_DSIn_CK6 CK) (0)) (HOLD DQSNeg (COND ChHold_DS_CK3 CK) (1)) (HOLD DQSNeg (COND ChHold_DS_CK4 CK) (1)) (HOLD DQSNeg (COND ChHold_DS_CK5 CK) (0)) (HOLD DQSNeg (COND ChHold_DS_CK6 CK) (0)) (WIDTH (COND ChEnable_CK3 CK)(2.4)) (WIDTH (COND ChEnable_CK4 CK)(2.4)) (WIDTH (COND ChEnable_CK5 CK)(0)) (WIDTH (COND ChEnable_CK6 CK)(0)) (WIDTH (COND (CL3 == 1) BA0)(3)) (WIDTH (COND (CL3 == 1) BA1)(3)) (WIDTH (COND (CL3 == 1) BA2)(3)) (WIDTH (COND (CL4 == 1) BA0)(3)) (WIDTH (COND (CL4 == 1) BA1)(3)) (WIDTH (COND (CL4 == 1) BA2)(3)) (WIDTH (COND (CL5 == 1) BA0)(0)) (WIDTH (COND (CL5 == 1) BA1)(0)) (WIDTH (COND (CL5 == 1) BA2)(0)) (WIDTH (COND (CL6 == 1) BA0)(0)) (WIDTH (COND (CL6 == 1) BA1)(0)) (WIDTH (COND (CL6 == 1) BA2)(0)) (WIDTH (COND (CL3 == 1) BA0)(3)) (WIDTH (COND (CL3 == 1) A1)(3)) (WIDTH (COND (CL3 == 1) A2)(3)) (WIDTH (COND (CL3 == 1) A3)(3)) (WIDTH (COND (CL3 == 1) A4)(3)) (WIDTH (COND (CL3 == 1) A5)(3)) (WIDTH (COND (CL3 == 1) A6)(3)) (WIDTH (COND (CL3 == 1) A7)(3)) (WIDTH (COND (CL3 == 1) A8)(3)) (WIDTH (COND (CL3 == 1) A9)(3)) (WIDTH (COND (CL3 == 1) A10)(3)) (WIDTH (COND (CL3 == 1) A11)(3)) (WIDTH (COND (CL3 == 1) A12)(3)) (WIDTH (COND (CL3 == 1) A13)(3)) (WIDTH (COND (CL4 == 1) A0)(3)) (WIDTH (COND (CL4 == 1) A1)(3)) (WIDTH (COND (CL4 == 1) A2)(3)) (WIDTH (COND (CL4 == 1) A3)(3)) (WIDTH (COND (CL4 == 1) A4)(3)) (WIDTH (COND (CL4 == 1) A5)(3)) (WIDTH (COND (CL4 == 1) A6)(3)) (WIDTH (COND (CL4 == 1) A7)(3)) (WIDTH (COND (CL4 == 1) A8)(3)) (WIDTH (COND (CL4 == 1) A9)(3)) (WIDTH (COND (CL4 == 1) A10)(3)) (WIDTH (COND (CL4 == 1) A11)(3)) (WIDTH (COND (CL4 == 1) A12)(3)) (WIDTH (COND (CL4 == 1) A13)(3)) (WIDTH (COND (CL5 == 1) A0)(0)) (WIDTH (COND (CL5 == 1) A1)(0)) (WIDTH (COND (CL5 == 1) A2)(0)) (WIDTH (COND (CL5 == 1) A3)(0)) (WIDTH (COND (CL5 == 1) A4)(0)) (WIDTH (COND (CL5 == 1) A5)(0)) (WIDTH (COND (CL5 == 1) A6)(0)) (WIDTH (COND (CL5 == 1) A7)(0)) (WIDTH (COND (CL5 == 1) A8)(0)) (WIDTH (COND (CL5 == 1) A9)(0)) (WIDTH (COND (CL5 == 1) A10)(0)) (WIDTH (COND (CL5 == 1) A11)(0)) (WIDTH (COND (CL5 == 1) A12)(0)) (WIDTH (COND (CL5 == 1) A13)(0)) (WIDTH (COND (CL6 == 1) A0)(0)) (WIDTH (COND (CL6 == 1) A1)(0)) (WIDTH (COND (CL6 == 1) A2)(0)) (WIDTH (COND (CL6 == 1) A3)(0)) (WIDTH (COND (CL6 == 1) A4)(0)) (WIDTH (COND (CL6 == 1) A5)(0)) (WIDTH (COND (CL6 == 1) A6)(0)) (WIDTH (COND (CL6 == 1) A7)(0)) (WIDTH (COND (CL6 == 1) A8)(0)) (WIDTH (COND (CL6 == 1) A9)(0)) (WIDTH (COND (CL6 == 1) A10)(0)) (WIDTH (COND (CL6 == 1) A11)(0)) (WIDTH (COND (CL6 == 1) A12)(0)) (WIDTH (COND (CL6 == 1) A13)(0)) (WIDTH (COND (CL3 == 1) DQ0)(1.75)) (WIDTH (COND (CL3 == 1) DQ1)(1.75)) (WIDTH (COND (CL3 == 1) DQ2)(1.75)) (WIDTH (COND (CL3 == 1) DQ3)(1.75)) (WIDTH (COND (CL3 == 1) DQ4)(1.75)) (WIDTH (COND (CL3 == 1) DQ5)(1.75)) (WIDTH (COND (CL3 == 1) DQ6)(1.75)) (WIDTH (COND (CL3 == 1) DQ7)(1.75)) (WIDTH (COND (CL4 == 1) DQ0)(1.75)) (WIDTH (COND (CL4 == 1) DQ1)(1.75)) (WIDTH (COND (CL4 == 1) DQ2)(1.75)) (WIDTH (COND (CL4 == 1) DQ3)(1.75)) (WIDTH (COND (CL4 == 1) DQ4)(1.75)) (WIDTH (COND (CL4 == 1) DQ5)(1.75)) (WIDTH (COND (CL4 == 1) DQ6)(1.75)) (WIDTH (COND (CL4 == 1) DQ7)(1.75)) (WIDTH (COND (CL5 == 1) DQ0)(0)) (WIDTH (COND (CL5 == 1) DQ1)(0)) (WIDTH (COND (CL5 == 1) DQ2)(0)) (WIDTH (COND (CL5 == 1) DQ3)(0)) (WIDTH (COND (CL5 == 1) DQ4)(0)) (WIDTH (COND (CL5 == 1) DQ5)(0)) (WIDTH (COND (CL5 == 1) DQ6)(0)) (WIDTH (COND (CL5 == 1) DQ7)(0)) (WIDTH (COND (CL6 == 1) DQ0)(0)) (WIDTH (COND (CL6 == 1) DQ1)(0)) (WIDTH (COND (CL6 == 1) DQ2)(0)) (WIDTH (COND (CL6 == 1) DQ3)(0)) (WIDTH (COND (CL6 == 1) DQ4)(0)) (WIDTH (COND (CL6 == 1) DQ5)(0)) (WIDTH (COND (CL6 == 1) DQ6)(0)) (WIDTH (COND (CL6 == 1) DQ7)(0)) (WIDTH (COND (DM3 == 1) RDQS)(1.75)) (WIDTH (COND (DM4 == 1) RDQS)(1.75)) (WIDTH (COND (DM5 == 1) RDQS)(0)) (WIDTH (COND (DM6 == 1) RDQS)(0)) (WIDTH (COND (CL3 == 1) ODT)(1.75)) (WIDTH (COND (CL4 == 1) ODT)(1.75)) (WIDTH (COND (CL5 == 1) ODT)(0)) (WIDTH (COND (CL6 == 1) ODT)(0)) (WIDTH (COND (CL3 == 1) CSNeg)(1.75)) (WIDTH (COND (CL4 == 1) CSNeg)(1.75)) (WIDTH (COND (CL5 == 1) CSNeg)(0)) (WIDTH (COND (CL6 == 1) CSNeg)(0)) (WIDTH (COND (CL3 == 1) RASNeg)(1.75)) (WIDTH (COND (CL4 == 1) RASNeg)(1.75)) (WIDTH (COND (CL5 == 1) RASNeg)(0)) (WIDTH (COND (CL6 == 1) RASNeg)(0)) (WIDTH (COND (CL3 == 1) CASNeg)(1.75)) (WIDTH (COND (CL4 == 1) CASNeg)(1.75)) (WIDTH (COND (CL5 == 1) CASNeg)(0)) (WIDTH (COND (CL6 == 1) CASNeg)(0)) (WIDTH (COND (CL3 == 1) WENeg)(1.75)) (WIDTH (COND (CL4 == 1) WENeg)(1.75)) (WIDTH (COND (CL5 == 1) WENeg)(0)) (WIDTH (COND (CL6 == 1) WENeg)(0)) (WIDTH (COND ChNormalCL3 (posedge DQS))(1.75)) (WIDTH (COND ChNormalCL3 (negedge DQS))(1.75)) (WIDTH (COND ChNormalCL4 (posedge DQS))(1.75)) (WIDTH (COND ChNormalCL4 (negedge DQS))(1.75)) (WIDTH (COND ChNormalCL5 (posedge DQS))(0)) (WIDTH (COND ChNormalCL5 (negedge DQS))(0)) (WIDTH (COND ChNormalCL6 (posedge DQS))(0)) (WIDTH (COND ChNormalCL6 (negedge DQS))(0)) (WIDTH (COND ChPreambleCL3 (negedge DQS))(1.25)) (WIDTH (COND ChPreambleCL4 (negedge DQS))(1.25)) (WIDTH (COND ChPreambleCL5 (negedge DQS))(0)) (WIDTH (COND ChPreambleCL6 (negedge DQS))(0)) (WIDTH (COND ChPostambleCL3 (negedge DQS))(2)) (WIDTH (COND ChPostambleCL4 (negedge DQS))(2)) (WIDTH (COND ChPostambleCL5 (negedge DQS))(0)) (WIDTH (COND ChPostambleCL6 (negedge DQS))(0)) (WIDTH (COND ChDQSNegCL3 (posedge DQSNeg))(1.75)) (WIDTH (COND ChDQSNegCL3 (negedge DQSNeg))(1.75)) (WIDTH (COND ChDQSNegCL4 (posedge DQSNeg))(1.75)) (WIDTH (COND ChDQSNegCL4 (negedge DQSNeg))(1.75)) (WIDTH (COND ChDQSNegCL5 (posedge DQSNeg))(0)) (WIDTH (COND ChDQSNegCL5 (negedge DQSNeg))(0)) (WIDTH (COND ChDQSNegCL6 (posedge DQSNeg))(0)) (WIDTH (COND ChDQSNegCL6 (negedge DQSNeg))(0)) (WIDTH (COND CheckPreambleCL3 (posedge DQSNeg))(1.25)) (WIDTH (COND CheckPreambleCL4 (posedge DQSNeg))(1.25)) (WIDTH (COND CheckPreambleCL5 (posedge DQSNeg))(0)) (WIDTH (COND CheckPreambleCL6 (posedge DQSNeg))(0)) (WIDTH (COND CheckPostambleCL3 (posedge DQSNeg))(2)) (WIDTH (COND CheckPostambleCL4 (posedge DQSNeg))(2)) (WIDTH (COND CheckPostambleCL5 (posedge DQSNeg))(0)) (WIDTH (COND CheckPostambleCL6 (posedge DQSNeg))(0)) (PERIOD (COND ChEnable_CK3 CK) (5)) (PERIOD (COND ChEnable_CK4 CK) (5)) (PERIOD (COND ChEnable_CK5 CK) (0)) (PERIOD (COND ChEnable_CK6 CK) (0)) )) (CELL (CELLTYPE "BUFFER") (INSTANCE dut/BUFSKEW) (DELAY (ABSOLUTE (DEVICE OUT (1.25:1.25:1.25))))) (CELL (CELLTYPE "BUFFER") (INSTANCE %LABEL%/BUFDLL) (DELAY (ABSOLUTE (DEVICE OUT (0.6:0.6:0.6)))) MT47H128M8BT-25Micron Technology Inc, pdf:09005aef8117c1b1, source:09005aef8117c192 1GbDDR2_2.fm - Rev. H 11/05 EN MT47H128M8BT-25ITMicron Technology Inc, pdf:09005aef8117c1b1, source:09005aef8117c192 1GbDDR2_2.fm - Rev. H 11/05 EN MT47H128M8BT-25LMicron Technology Inc, pdf:09005aef8117c1b1, source:09005aef8117c192 1GbDDR2_2.fm - Rev. H 11/05 EN MT47H128M8BT-25LITMicron Technology Inc, pdf:09005aef8117c1b1, source:09005aef8117c192 1GbDDR2_2.fm - Rev. H 11/05 EN The values listed are for VDD = +1.8V ±0.1V (DELAY (ABSOLUTE (IOPATH CK DQ0 (0.4) (0.4) (0.4) (0.4) (0.4) (0.4)) (IOPATH CK DQ1 (0.4) (0.4) (0.4) (0.4) (0.4) (0.4)) (IOPATH CK DQ2 (0.4) (0.4) (0.4) (0.4) (0.4) (0.4)) (IOPATH CK DQ3 (0.4) (0.4) (0.4) (0.4) (0.4) (0.4)) (IOPATH CK DQ4 (0.4) (0.4) (0.4) (0.4) (0.4) (0.4)) (IOPATH CK DQ5 (0.4) (0.4) (0.4) (0.4) (0.4) (0.4)) (IOPATH CK DQ6 (0.4) (0.4) (0.4) (0.4) (0.4) (0.4)) (IOPATH CK DQ7 (0.4) (0.4) (0.4) (0.4) (0.4) (0.4)) (IOPATH CK DQS (0.35) (0.35) (0.35) (0.35) (0.35) (0.35)) (IOPATH CK RDQS (0.35) (0.35) (0.35) (0.35) (0.35) (0.35)) (IOPATH CK DQSNeg (0.35) (0.35) (0.35) (0.35) (0.35) (0.35)) (IOPATH CK RDQSNeg (0.35) (0.35) (0.35) (0.35) (0.35) (0.35)) )) (TIMINGCHECK (SETUP DQ0 DQS (0.05)) (SETUP DQ1 DQS (0.05)) (SETUP DQ2 DQS (0.05)) (SETUP DQ3 DQS (0.05)) (SETUP DQ4 DQS (0.05)) (SETUP DQ5 DQS (0.05)) (SETUP DQ6 DQS (0.05)) (SETUP DQ7 DQS (0.05)) (SETUP DQ0 DQSNeg (0.05)) (SETUP DQ1 DQSNeg (0.05)) (SETUP DQ2 DQSNeg (0.05)) (SETUP DQ3 DQSNeg (0.05)) (SETUP DQ4 DQSNeg (0.05)) (SETUP DQ5 DQSNeg (0.05)) (SETUP DQ6 DQSNeg (0.05)) (SETUP DQ7 DQSNeg (0.05)) (SETUP RDQS DQS (0.05)) (SETUP RDQS DQSNeg (0.05)) (SETUP ODT CK (0.2)) (SETUP CKE CK (0.2)) (SETUP CSNeg CK (0.2)) (SETUP RASNeg CK (0.2)) (SETUP CASNeg CK (0.2)) (SETUP WENeg CK (0.2)) (SETUP BA0 CK (0.2)) (SETUP BA1 CK (0.2)) (SETUP BA2 CK (0.2)) (SETUP A0 CK (0.2)) (SETUP A1 CK (0.2)) (SETUP A2 CK (0.2)) (SETUP A3 CK (0.2)) (SETUP A4 CK (0.2)) (SETUP A5 CK (0.2)) (SETUP A6 CK (0.2)) (SETUP A7 CK (0.2)) (SETUP A8 CK (0.2)) (SETUP A9 CK (0.2)) (SETUP A10 CK (0.2)) (SETUP A11 CK (0.2)) (SETUP A12 CK (0.2)) (SETUP A13 CK (0.2)) (SETUP DQS (COND ChSetup_DSIn_CK3 CK) (0)) (SETUP DQS (COND ChSetup_DSIn_CK4 CK) (0)) (SETUP DQS (COND ChSetup_DSIn_CK5 CK) (0.6)) (SETUP DQS (COND ChSetup_DSIn_CK6 CK) (0.5)) (SETUP DQSNeg (COND ChSetup_DS_CK3 CK) (0)) (SETUP DQSNeg (COND ChSetup_DS_CK4 CK) (0)) (SETUP DQSNeg (COND ChSetup_DS_CK5 CK) (0.6)) (SETUP DQSNeg (COND ChSetup_DS_CK6 CK) (0.5)) (HOLD DQ0 DQS (0.125)) (HOLD DQ1 DQS (0.125)) (HOLD DQ2 DQS (0.125)) (HOLD DQ3 DQS (0.125)) (HOLD DQ4 DQS (0.125)) (HOLD DQ5 DQS (0.125)) (HOLD DQ6 DQS (0.125)) (HOLD DQ7 DQS (0.125)) (HOLD DQ0 DQSNeg (0.125)) (HOLD DQ1 DQSNeg (0.125)) (HOLD DQ2 DQSNeg (0.125)) (HOLD DQ3 DQSNeg (0.125)) (HOLD DQ4 DQSNeg (0.125)) (HOLD DQ5 DQSNeg (0.125)) (HOLD DQ6 DQSNeg (0.125)) (HOLD DQ7 DQSNeg (0.125)) (HOLD RDQS DQS (0.125)) (HOLD RDQS DQSNeg (0.125)) (HOLD ODT CK (0.275)) (HOLD CKE CK (0.275)) (HOLD CSNeg CK (0.275)) (HOLD RASNeg CK (0.275)) (HOLD CASNeg CK (0.275)) (HOLD WENeg CK (0.275)) (HOLD BA0 CK (0.275)) (HOLD BA1 CK (0.275)) (HOLD BA2 CK (0.275)) (HOLD A0 CK (0.275)) (HOLD A1 CK (0.275)) (HOLD A2 CK (0.275)) (HOLD A3 CK (0.275)) (HOLD A4 CK (0.275)) (HOLD A5 CK (0.275)) (HOLD A6 CK (0.275)) (HOLD A7 CK (0.275)) (HOLD A8 CK (0.275)) (HOLD A9 CK (0.275)) (HOLD A10 CK (0.275)) (HOLD A11 CK (0.275)) (HOLD A12 CK (0.275)) (HOLD A13 CK (0.275)) (HOLD DQS (COND ChHold_DSIn_CK3 CK) (0)) (HOLD DQS (COND ChHold_DSIn_CK4 CK) (0)) (HOLD DQS (COND ChHold_DSIn_CK5 CK) (0.6)) (HOLD DQS (COND ChHold_DSIn_CK6 CK) (0.5)) (HOLD DQSNeg (COND ChHold_DS_CK3 CK) (0)) (HOLD DQSNeg (COND ChHold_DS_CK4 CK) (0)) (HOLD DQSNeg (COND ChHold_DS_CK5 CK) (0.6)) (HOLD DQSNeg (COND ChHold_DS_CK6 CK) (0.5)) (WIDTH (COND ChEnable_CK3 CK)(0)) (WIDTH (COND ChEnable_CK4 CK)(0)) (WIDTH (COND ChEnable_CK5 CK)(1.44)) (WIDTH (COND ChEnable_CK6 CK)(1.2)) (WIDTH (COND (CL3 == 1) A0)(0)) (WIDTH (COND (CL3 == 1) A1)(0)) (WIDTH (COND (CL3 == 1) A2)(0)) (WIDTH (COND (CL3 == 1) A3)(0)) (WIDTH (COND (CL3 == 1) A4)(0)) (WIDTH (COND (CL3 == 1) A5)(0)) (WIDTH (COND (CL3 == 1) A6)(0)) (WIDTH (COND (CL3 == 1) A7)(0)) (WIDTH (COND (CL3 == 1) A8)(0)) (WIDTH (COND (CL3 == 1) A9)(0)) (WIDTH (COND (CL3 == 1) A10)(0)) (WIDTH (COND (CL3 == 1) A11)(0)) (WIDTH (COND (CL3 == 1) A12)(0)) (WIDTH (COND (CL3 == 1) A13)(0)) (WIDTH (COND (CL4 == 1) A0)(0)) (WIDTH (COND (CL4 == 1) A1)(0)) (WIDTH (COND (CL4 == 1) A2)(0)) (WIDTH (COND (CL4 == 1) A3)(0)) (WIDTH (COND (CL4 == 1) A4)(0)) (WIDTH (COND (CL4 == 1) A5)(0)) (WIDTH (COND (CL4 == 1) A6)(0)) (WIDTH (COND (CL4 == 1) A7)(0)) (WIDTH (COND (CL4 == 1) A8)(0)) (WIDTH (COND (CL4 == 1) A9)(0)) (WIDTH (COND (CL4 == 1) A10)(0)) (WIDTH (COND (CL4 == 1) A11)(0)) (WIDTH (COND (CL4 == 1) A12)(0)) (WIDTH (COND (CL4 == 1) A13)(0)) (WIDTH (COND (CL5 == 1) A0)(1.8)) (WIDTH (COND (CL5 == 1) A1)(1.8)) (WIDTH (COND (CL5 == 1) A2)(1.8)) (WIDTH (COND (CL5 == 1) A3)(1.8)) (WIDTH (COND (CL5 == 1) A4)(1.8)) (WIDTH (COND (CL5 == 1) A5)(1.8)) (WIDTH (COND (CL5 == 1) A6)(1.8)) (WIDTH (COND (CL5 == 1) A7)(1.8)) (WIDTH (COND (CL5 == 1) A8)(1.8)) (WIDTH (COND (CL5 == 1) A9)(1.8)) (WIDTH (COND (CL5 == 1) A10)(1.8)) (WIDTH (COND (CL5 == 1) A11)(1.8)) (WIDTH (COND (CL5 == 1) A12)(1.8)) (WIDTH (COND (CL5 == 1) A13)(1.8)) (WIDTH (COND (CL6 == 1) A0)(1.5)) (WIDTH (COND (CL6 == 1) A1)(1.5)) (WIDTH (COND (CL6 == 1) A2)(1.5)) (WIDTH (COND (CL6 == 1) A3)(1.5)) (WIDTH (COND (CL6 == 1) A4)(1.5)) (WIDTH (COND (CL6 == 1) A5)(1.5)) (WIDTH (COND (CL6 == 1) A6)(1.5)) (WIDTH (COND (CL6 == 1) A7)(1.5)) (WIDTH (COND (CL6 == 1) A8)(1.5)) (WIDTH (COND (CL6 == 1) A9)(1.5)) (WIDTH (COND (CL6 == 1) A10)(1.5)) (WIDTH (COND (CL6 == 1) A11)(1.5)) (WIDTH (COND (CL6 == 1) A12)(1.5)) (WIDTH (COND (CL6 == 1) A13)(1.5)) (WIDTH (COND (CL3 == 1) DQ0)(0)) (WIDTH (COND (CL3 == 1) DQ1)(0)) (WIDTH (COND (CL3 == 1) DQ2)(0)) (WIDTH (COND (CL3 == 1) DQ3)(0)) (WIDTH (COND (CL3 == 1) DQ4)(0)) (WIDTH (COND (CL3 == 1) DQ5)(0)) (WIDTH (COND (CL3 == 1) DQ6)(0)) (WIDTH (COND (CL3 == 1) DQ7)(0)) (WIDTH (COND (CL4 == 1) DQ0)(0)) (WIDTH (COND (CL4 == 1) DQ1)(0)) (WIDTH (COND (CL4 == 1) DQ2)(0)) (WIDTH (COND (CL4 == 1) DQ3)(0)) (WIDTH (COND (CL4 == 1) DQ4)(0)) (WIDTH (COND (CL4 == 1) DQ5)(0)) (WIDTH (COND (CL4 == 1) DQ6)(0)) (WIDTH (COND (CL4 == 1) DQ7)(0)) (WIDTH (COND (CL5 == 1) DQ0)(1.05)) (WIDTH (COND (CL5 == 1) DQ1)(1.05)) (WIDTH (COND (CL5 == 1) DQ2)(1.05)) (WIDTH (COND (CL5 == 1) DQ3)(1.05)) (WIDTH (COND (CL5 == 1) DQ4)(1.05)) (WIDTH (COND (CL5 == 1) DQ5)(1.05)) (WIDTH (COND (CL5 == 1) DQ6)(1.05)) (WIDTH (COND (CL5 == 1) DQ7)(1.05)) (WIDTH (COND (CL6 == 1) DQ0)(0.875)) (WIDTH (COND (CL6 == 1) DQ1)(0.875)) (WIDTH (COND (CL6 == 1) DQ2)(0.875)) (WIDTH (COND (CL6 == 1) DQ3)(0.875)) (WIDTH (COND (CL6 == 1) DQ4)(0.875)) (WIDTH (COND (CL6 == 1) DQ5)(0.875)) (WIDTH (COND (CL6 == 1) DQ6)(0.875)) (WIDTH (COND (CL6 == 1) DQ7)(0.875)) (WIDTH (COND (DM3 == 1) RDQS)(0)) (WIDTH (COND (DM4 == 1) RDQS)(0)) (WIDTH (COND (DM5 == 1) RDQS)(1.05)) (WIDTH (COND (DM6 == 1) RDQS)(0.875)) (WIDTH (COND (CL3 == 1) ODT)(0)) (WIDTH (COND (CL4 == 1) ODT)(0)) (WIDTH (COND (CL5 == 1) ODT)(1.05)) (WIDTH (COND (CL6 == 1) ODT)(0.875)) (WIDTH (COND (CL3 == 1) CSNeg)(0)) (WIDTH (COND (CL4 == 1) CSNeg)(0)) (WIDTH (COND (CL5 == 1) CSNeg)(1.05)) (WIDTH (COND (CL6 == 1) CSNeg)(0.875)) (WIDTH (COND (CL3 == 1) RASNeg)(0)) (WIDTH (COND (CL4 == 1) RASNeg)(0)) (WIDTH (COND (CL5 == 1) RASNeg)(1.05)) (WIDTH (COND (CL6 == 1) RASNeg)(0.875)) (WIDTH (COND (CL3 == 1) CASNeg)(0)) (WIDTH (COND (CL4 == 1) CASNeg)(0)) (WIDTH (COND (CL5 == 1) CASNeg)(1.05)) (WIDTH (COND (CL6 == 1) CASNeg)(0.875)) (WIDTH (COND (CL3 == 1) WENeg)(0)) (WIDTH (COND (CL4 == 1) WENeg)(0)) (WIDTH (COND (CL5 == 1) WENeg)(1.05)) (WIDTH (COND (CL6 == 1) WENeg)(0.875)) (WIDTH (COND ChNormalCL3 (posedge DQS))(0)) (WIDTH (COND ChNormalCL3 (negedge DQS))(0)) (WIDTH (COND ChNormalCL4 (posedge DQS))(0)) (WIDTH (COND ChNormalCL4 (negedge DQS))(0)) (WIDTH (COND ChNormalCL5 (posedge DQS))(1.05)) (WIDTH (COND ChNormalCL5 (negedge DQS))(1.05)) (WIDTH (COND ChNormalCL6 (posedge DQS))(0.875)) (WIDTH (COND ChNormalCL6 (negedge DQS))(0.875)) (WIDTH (COND ChPreambleCL3 (negedge DQS))(0)) (WIDTH (COND ChPreambleCL4 (negedge DQS))(0)) (WIDTH (COND ChPreambleCL5 (negedge DQS))(1.05)) (WIDTH (COND ChPreambleCL6 (negedge DQS))(0.875)) (WIDTH (COND ChPostambleCL3 (negedge DQS))(0)) (WIDTH (COND ChPostambleCL4 (negedge DQS))(0)) (WIDTH (COND ChPostambleCL5 (negedge DQS))(1.2)) (WIDTH (COND ChPostambleCL6 (negedge DQS))(1)) (WIDTH (COND ChDQSNegCL3 (posedge DQSNeg))(0)) (WIDTH (COND ChDQSNegCL3 (negedge DQSNeg))(0)) (WIDTH (COND ChDQSNegCL4 (posedge DQSNeg))(0)) (WIDTH (COND ChDQSNegCL4 (negedge DQSNeg))(0)) (WIDTH (COND ChDQSNegCL5 (posedge DQSNeg))(1.05)) (WIDTH (COND ChDQSNegCL5 (negedge DQSNeg))(1.05)) (WIDTH (COND ChDQSNegCL6 (posedge DQSNeg))(0.875)) (WIDTH (COND ChDQSNegCL6 (negedge DQSNeg))(0.875)) (WIDTH (COND CheckPreambleCL3 (posedge DQSNeg))(0)) (WIDTH (COND CheckPreambleCL4 (posedge DQSNeg))(0)) (WIDTH (COND CheckPreambleCL5 (posedge DQSNeg))(1.05)) (WIDTH (COND CheckPreambleCL6 (posedge DQSNeg))(0.875)) (WIDTH (COND CheckPostambleCL3 (posedge DQSNeg))(0)) (WIDTH (COND CheckPostambleCL4 (posedge DQSNeg))(0)) (WIDTH (COND CheckPostambleCL5 (posedge DQSNeg))(1.2)) (WIDTH (COND CheckPostambleCL6 (posedge DQSNeg))(1)) (PERIOD (COND ChEnable_CK3 CK) (0)) (PERIOD (COND ChEnable_CK4 CK) (0)) (PERIOD (COND ChEnable_CK5 CK) (3)) (PERIOD (COND ChEnable_CK6 CK) (2.5)) )) (CELL (CELLTYPE "BUFFER") (INSTANCE dut/BUFSKEW) (DELAY (ABSOLUTE (DEVICE OUT (0.625:0.625:0.625))))) (CELL (CELLTYPE "BUFFER") (INSTANCE %LABEL%/BUFDLL) (DELAY (ABSOLUTE (DEVICE OUT (0.4:0.4:0.4)))) MT47H128M8BT-25EMicron Technology Inc, pdf:09005aef8117c1b1, source:09005aef8117c192 1GbDDR2_2.fm - Rev. H 11/05 EN MT47H128M8BT-25EITMicron Technology Inc, pdf:09005aef8117c1b1, source:09005aef8117c192 1GbDDR2_2.fm - Rev. H 11/05 EN MT47H128M8BT-25ELMicron Technology Inc, pdf:09005aef8117c1b1, source:09005aef8117c192 1GbDDR2_2.fm - Rev. H 11/05 EN MT47H128M8BT-25ELITMicron Technology Inc, pdf:09005aef8117c1b1, source:09005aef8117c192 1GbDDR2_2.fm - Rev. H 11/05 EN The values listed are for VDD = +1.8V ±0.1V (DELAY (ABSOLUTE (IOPATH CK DQ0 (0.4) (0.4) (0.4) (0.4) (0.4) (0.4)) (IOPATH CK DQ1 (0.4) (0.4) (0.4) (0.4) (0.4) (0.4)) (IOPATH CK DQ2 (0.4) (0.4) (0.4) (0.4) (0.4) (0.4)) (IOPATH CK DQ3 (0.4) (0.4) (0.4) (0.4) (0.4) (0.4)) (IOPATH CK DQ4 (0.4) (0.4) (0.4) (0.4) (0.4) (0.4)) (IOPATH CK DQ5 (0.4) (0.4) (0.4) (0.4) (0.4) (0.4)) (IOPATH CK DQ6 (0.4) (0.4) (0.4) (0.4) (0.4) (0.4)) (IOPATH CK DQ7 (0.4) (0.4) (0.4) (0.4) (0.4) (0.4)) (IOPATH CK DQS (0.35) (0.35) (0.35) (0.35) (0.35) (0.35)) (IOPATH CK RDQS (0.35) (0.35) (0.35) (0.35) (0.35) (0.35)) (IOPATH CK DQSNeg (0.35) (0.35) (0.35) (0.35) (0.35) (0.35)) (IOPATH CK RDQSNeg (0.35) (0.35) (0.35) (0.35) (0.35) (0.35)) )) (TIMINGCHECK (SETUP DQ0 DQS (0.05)) (SETUP DQ1 DQS (0.05)) (SETUP DQ2 DQS (0.05)) (SETUP DQ3 DQS (0.05)) (SETUP DQ4 DQS (0.05)) (SETUP DQ5 DQS (0.05)) (SETUP DQ6 DQS (0.05)) (SETUP DQ7 DQS (0.05)) (SETUP DQ0 DQSNeg (0.05)) (SETUP DQ1 DQSNeg (0.05)) (SETUP DQ2 DQSNeg (0.05)) (SETUP DQ3 DQSNeg (0.05)) (SETUP DQ4 DQSNeg (0.05)) (SETUP DQ5 DQSNeg (0.05)) (SETUP DQ6 DQSNeg (0.05)) (SETUP DQ7 DQSNeg (0.05)) (SETUP RDQS DQS (0.05)) (SETUP RDQS DQSNeg (0.05)) (SETUP ODT CK (0.2)) (SETUP CKE CK (0.2)) (SETUP CSNeg CK (0.2)) (SETUP RASNeg CK (0.2)) (SETUP CASNeg CK (0.2)) (SETUP WENeg CK (0.2)) (SETUP BA0 CK (0.2)) (SETUP BA1 CK (0.2)) (SETUP BA2 CK (0.2)) (SETUP A0 CK (0.2)) (SETUP A1 CK (0.2)) (SETUP A2 CK (0.2)) (SETUP A3 CK (0.2)) (SETUP A4 CK (0.2)) (SETUP A5 CK (0.2)) (SETUP A6 CK (0.2)) (SETUP A7 CK (0.2)) (SETUP A8 CK (0.2)) (SETUP A9 CK (0.2)) (SETUP A10 CK (0.2)) (SETUP A11 CK (0.2)) (SETUP A12 CK (0.2)) (SETUP A13 CK (0.2)) (SETUP DQS (COND ChSetup_DSIn_CK3 CK) (0)) (SETUP DQS (COND ChSetup_DSIn_CK4 CK) (0.75)) (SETUP DQS (COND ChSetup_DSIn_CK5 CK) (0.5)) (SETUP DQS (COND ChSetup_DSIn_CK6 CK) (0)) (SETUP DQSNeg (COND ChSetup_DS_CK3 CK) (0)) (SETUP DQSNeg (COND ChSetup_DS_CK4 CK) (0.75)) (SETUP DQSNeg (COND ChSetup_DS_CK5 CK) (0.5)) (SETUP DQSNeg (COND ChSetup_DS_CK6 CK) (0)) (HOLD DQ0 DQS (0.125)) (HOLD DQ1 DQS (0.125)) (HOLD DQ2 DQS (0.125)) (HOLD DQ3 DQS (0.125)) (HOLD DQ4 DQS (0.125)) (HOLD DQ5 DQS (0.125)) (HOLD DQ6 DQS (0.125)) (HOLD DQ7 DQS (0.125)) (HOLD DQ0 DQSNeg (0.125)) (HOLD DQ1 DQSNeg (0.125)) (HOLD DQ2 DQSNeg (0.125)) (HOLD DQ3 DQSNeg (0.125)) (HOLD DQ4 DQSNeg (0.125)) (HOLD DQ5 DQSNeg (0.125)) (HOLD DQ6 DQSNeg (0.125)) (HOLD DQ7 DQSNeg (0.125)) (HOLD RDQS DQS (0.125)) (HOLD RDQS DQSNeg (0.125)) (HOLD ODT CK (0.275)) (HOLD CKE CK (0.275)) (HOLD CSNeg CK (0.275)) (HOLD RASNeg CK (0.275)) (HOLD CASNeg CK (0.275)) (HOLD WENeg CK (0.275)) (HOLD BA0 CK (0.275)) (HOLD BA1 CK (0.275)) (HOLD BA2 CK (0.275)) (HOLD A0 CK (0.275)) (HOLD A1 CK (0.275)) (HOLD A2 CK (0.275)) (HOLD A3 CK (0.275)) (HOLD A4 CK (0.275)) (HOLD A5 CK (0.275)) (HOLD A6 CK (0.275)) (HOLD A7 CK (0.275)) (HOLD A8 CK (0.275)) (HOLD A9 CK (0.275)) (HOLD A10 CK (0.275)) (HOLD A11 CK (0.275)) (HOLD A12 CK (0.275)) (HOLD A13 CK (0.275)) (HOLD DQS (COND ChHold_DSIn_CK3 CK) (0)) (HOLD DQS (COND ChHold_DSIn_CK4 CK) (0.75)) (HOLD DQS (COND ChHold_DSIn_CK5 CK) (0.5)) (HOLD DQS (COND ChHold_DSIn_CK6 CK) (0)) (HOLD DQSNeg (COND ChHold_DS_CK3 CK) (0)) (HOLD DQSNeg (COND ChHold_DS_CK4 CK) (0.75)) (HOLD DQSNeg (COND ChHold_DS_CK5 CK) (0.5)) (HOLD DQSNeg (COND ChHold_DS_CK6 CK) (0)) (WIDTH (COND ChEnable_CK3 CK)(0)) (WIDTH (COND ChEnable_CK4 CK)(1.8)) (WIDTH (COND ChEnable_CK5 CK)(1.2)) (WIDTH (COND ChEnable_CK6 CK)(0)) (WIDTH (COND (CL3 == 1) BA0)(0)) (WIDTH (COND (CL3 == 1) BA1)(0)) (WIDTH (COND (CL3 == 1) BA2)(0)) (WIDTH (COND (CL4 == 1) BA0)(2.25)) (WIDTH (COND (CL4 == 1) BA1)(2.25)) (WIDTH (COND (CL4 == 1) BA2)(2.25)) (WIDTH (COND (CL5 == 1) BA0)(1.5)) (WIDTH (COND (CL5 == 1) BA1)(1.5)) (WIDTH (COND (CL5 == 1) BA2)(1.5)) (WIDTH (COND (CL6 == 1) BA0)(0)) (WIDTH (COND (CL6 == 1) BA1)(0)) (WIDTH (COND (CL6 == 1) BA2)(0)) (WIDTH (COND (CL3 == 1) A0)(0)) (WIDTH (COND (CL3 == 1) A1)(0)) (WIDTH (COND (CL3 == 1) A2)(0)) (WIDTH (COND (CL3 == 1) A3)(0)) (WIDTH (COND (CL3 == 1) A4)(0)) (WIDTH (COND (CL3 == 1) A5)(0)) (WIDTH (COND (CL3 == 1) A6)(0)) (WIDTH (COND (CL3 == 1) A7)(0)) (WIDTH (COND (CL3 == 1) A8)(0)) (WIDTH (COND (CL3 == 1) A9)(0)) (WIDTH (COND (CL3 == 1) A10)(0)) (WIDTH (COND (CL3 == 1) A11)(0)) (WIDTH (COND (CL3 == 1) A12)(0)) (WIDTH (COND (CL3 == 1) A13)(0)) (WIDTH (COND (CL4 == 1) A0)(2.25)) (WIDTH (COND (CL4 == 1) A1)(2.25)) (WIDTH (COND (CL4 == 1) A2)(2.25)) (WIDTH (COND (CL4 == 1) A3)(2.25)) (WIDTH (COND (CL4 == 1) A4)(2.25)) (WIDTH (COND (CL4 == 1) A5)(2.25)) (WIDTH (COND (CL4 == 1) A6)(2.25)) (WIDTH (COND (CL4 == 1) A7)(2.25)) (WIDTH (COND (CL4 == 1) A8)(2.25)) (WIDTH (COND (CL4 == 1) A9)(2.25)) (WIDTH (COND (CL4 == 1) A10)(2.25)) (WIDTH (COND (CL4 == 1) A11)(2.25)) (WIDTH (COND (CL4 == 1) A12)(2.25)) (WIDTH (COND (CL4 == 1) A13)(2.25)) (WIDTH (COND (CL5 == 1) A0)(1.5)) (WIDTH (COND (CL5 == 1) A1)(1.5)) (WIDTH (COND (CL5 == 1) A2)(1.5)) (WIDTH (COND (CL5 == 1) A3)(1.5)) (WIDTH (COND (CL5 == 1) A4)(1.5)) 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(COND (CL3 == 1) DQ7)(0)) (WIDTH (COND (CL4 == 1) DQ0)(1.312)) (WIDTH (COND (CL4 == 1) DQ1)(1.312)) (WIDTH (COND (CL4 == 1) DQ2)(1.312)) (WIDTH (COND (CL4 == 1) DQ3)(1.312)) (WIDTH (COND (CL4 == 1) DQ4)(1.312)) (WIDTH (COND (CL4 == 1) DQ5)(1.312)) (WIDTH (COND (CL4 == 1) DQ6)(1.312)) (WIDTH (COND (CL4 == 1) DQ7)(1.312)) (WIDTH (COND (CL5 == 1) DQ0)(0.875)) (WIDTH (COND (CL5 == 1) DQ1)(0.875)) (WIDTH (COND (CL5 == 1) DQ2)(0.875)) (WIDTH (COND (CL5 == 1) DQ3)(0.875)) (WIDTH (COND (CL5 == 1) DQ4)(0.875)) (WIDTH (COND (CL5 == 1) DQ5)(0.875)) (WIDTH (COND (CL5 == 1) DQ6)(0.875)) (WIDTH (COND (CL5 == 1) DQ7)(0.875)) (WIDTH (COND (CL6 == 1) DQ0)(0)) (WIDTH (COND (CL6 == 1) DQ1)(0)) (WIDTH (COND (CL6 == 1) DQ2)(0)) (WIDTH (COND (CL6 == 1) DQ3)(0)) (WIDTH (COND (CL6 == 1) DQ4)(0)) (WIDTH (COND (CL6 == 1) DQ5)(0)) (WIDTH (COND (CL6 == 1) DQ6)(0)) (WIDTH (COND (CL6 == 1) DQ7)(0)) (WIDTH (COND (DM3 == 1) RDQS)(0)) (WIDTH (COND (DM4 == 1) RDQS)(1.312)) (WIDTH (COND (DM5 == 1) RDQS)(0.875)) (WIDTH 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