The Model Library

Free Model Foundry


All the FMF models are VHDL'93 and VITAL'2000 compliant and require the VITAL'2000 library for correct compilation. They are designed for timing backannotation by means of an SDF file. The intrinsic delays default to 1 ns. We have a tool to read internal delays from an external file (in XML) and add them to the simulation through a SDF file. The most recent version is written in perl and may be downloaded from the "FMF Tools" area. Timing files are provided for over 19,800 part numbers.

Also in the tools area is the document type definition (dtd) for the timing files.


How models are copyrighted

Model List updated 2022 December 26

Individual models and timing files, may not be accessed directly from this page. Only entire libraries can be downloaded using the library links below. To download individual file or to view data sheets, use the Model List link above. Data sheets describe the models and what part numbers are covered in the timing files.

FMF Tools

FMF Packages (required for the models)


All libraries are available in tar'ed and compressed (gzip) format for easier downloading.

BUS Library

This is a collection of models of system buses that are used in board-level and system-level verification. They can be used to provide stimulus to portions of a design that include a particular bus interface.

CLOCK Library

This library contains clock generator and clock distribution models.

Converters VHDL Library

This library contains VHDL 1076 models of analog to digital and digital to analog converters. They use the VITAL packages but are not VITAL compliant.

ECL10 Library

The ECL10 Library contains models of 10K ECL parts available from several vendors.

ECL100 Library

The ECL100 Library contains models of 100K ECL parts available from several vendors.

ECLPS Library

The ECLPS Library contains models of the ECLinPS and ECLinPS Lite logic families from Motorola and Synergy.

FIFO Library

The FIFO Library is for models of various first-in-first-out memories. Most of these models were funded by Integrated Device Technology.

Flash Memory Library

This library is for flash memory models of components from Spansion, Intel and others.

Library of Generic SRAMs

This Library contains genric models of static random access memories. These models do not represent specific parts but are easy to customize for simulating particular components. Specific SRAM models will be placed in the RAM library.


These are drivers and receivers and sometimes, more complex models.

NLB Library

The NLB library contains models of a family of very high speed ECL parts from NTT Electronics Technology Corporation (NEL)

Processor Library

The models in the Processor library are of large, complex parts. Unless sponsored by the manufacturer, these models will often cover only those functional aspects that the funding organization required for their simulations. Because of the complexity of these models, this library is organized differently than the other libraries. Each model is supplied with a timing file, testbench, and other supporting files. All these files are tar'ed and compressed for a single download.

RAM Library

The RAM Library is for models of particular read/write memories. Because there is no generic number scheme for this class of parts, FMF will name models after a particular vendor's part number. We do not mean to play favorites with these numbers (except in the case of vendor sponsorship) - the vendor specific number will be chosen by the organization sponsoring the model. The timing files may still reflect multiple manufacturers.

STND Library

The STND Library contains models of 74XX/54XX parts available from a wide selection of vendors.

STNDH Library

This library contains parts of the same function as the STND library except these parts incorporate bus hold on their data inputs.

STNDS Library

The STNDS library contains models for a class of parts commonly called bus switches. Vendors usually number them as 74CBT or 74FST. Because they are bidirectional switches, they are very tough to model. A new package, switch_pkg, is required for them (see package library above). These models do not support timing on their data pins. We have, however, been able to add delays to their control pins. If anyone can come up with a better way of modeling this class of part, please let us know.


These are the sometimes tough, non-digital parts and other parts that don't fit into the other catagories.

We would like to hear of your experience using these models - the good, the bad, and the ugly. We would also like to hear which components, from which vendors, you need modeled. Please send email.

Contact Richard Munden: