VHDL-2008 Support Library

VHDL-2008 is finally getting some traction.   What started out as just a fixed and floating point package got merged into the largest addition to the VHDL language since it was started.   On this page you will find definitions of the functions available in the VHDL-2008 libraries. You will also find VHDL-93 compatible code for those that do not yet have access to VHDL-2008 compilers.

The VHDL-2008 packages will be included in your vendor's environment. In some cases I have found that they may be encrypted due to IEEE rules. The packages available on this page are NOT the released packages, but VHDL-93 versions of those packages, which I published BEFORE the release of the LRM. They are free of copyright restrictions, and may be used for whatever purpose is needed.

VHDL-93 versions of the VHDL-2008 packages

I use this code in most of my designs. Many times I find that I have to modify the code slightly in some tools, so I made this list. Included in the "source code" section for each tool is source code specifically debugged for that particluar tool. Click on the "documentation" link to see what changes I had to make, and how to use this code in the specific tool.

VendorZip fileNotes
Altera Source code (updated) Documentation
Cadence Source code (updated) Documentation
Modelsim Source code (updated) Documentation
Synopsys Source code (updated) Documentation
Synplicity Source code (updated) Documentation
Xilinx 11.1 Source code (updated) Documentation
Xilinx 9.1 Source code (old) Documentation
VCS Source code (updated) Documentation
Spectrum 2009a Source code Documentation
Do do:Aldec

Some helpful code to go with these packages:

  • fixed_noresize.vhdl Similar to "fixed_pkg", however this version uses the same rules that numeric_std does for the size of the result. This is done by calling the funciton in "fixed_pkg" and resizing the result.
  • float_noround_pkg.vhdl Similar to "float_pkg", however this version turns off all of the IEEE rounding and overflow, and defaults to a 26 bit floating point number. This package saves off 1/3 of the logic needed for full 32 bit floating point.
  • fixed_synth.vhdl Synthesis testcase for the fixed point package
  • test_fixed_synth.vhdl Testbench for the fixed point synthesis testcase.
  • float_synth.vhdl Synthesis testcase for the floating point package
  • test_float_synth.vhdl testbench for the floating point synthesis package

    Old version of this page

    Need some help with this code? Drop me an e-mail, maybe I can help.
    David W. Bishop dbishop@vhdl.org.   This web page is brought to you by the EDA Industry Working Groups and Accellera.