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	Web	FMF

Technical Papers on Component Modeling

New papers get added to the bottom of the list

Tricks and Techniques for Writing VITAL 3.0 Compliant ECL Models

Originally presented by Russ Vreeland at the 1996 International Cadence Users Group Conference. You may also download the pdf version.

Board-level Component Modeling Using VITAL

Originally presented by Russ Vreeland at the 1997 IVC/VIUF conference. You may also download the pdf version.

Integrating FMF Models with Concept Libraries

Originally presented by Richard Munden at the 1996 International Cadence Users Group Conference. You may also download the pdf version.

Connecting the System to the Chip

Presented by Russ Vreeland at the 1997 High Speed Electronic Systems Design Conference. This paper explains our use of VITAL for component modeling. You may also download the pdf version.

Style Guide for Simulation Models Written for the FMF Library Data Base

Second draft of the FMF Style Guide. Updated 99 MAR 27. Written by Raymond Steele. There are many advantages to using the FMF style for modeling components. This paper tells how and why. It is recommended that serious users download the pdf version. It contains some formatting that did not translate to html. It is in four files:
Title page,
Table of contents,
Body, and
Appendix A

Building an Environment for Mixed VHDL/Verilog Board-Level Simulation

Originally presented by Richard Munden at the 1998 International Cadence Users Group Conference. You may also download the pdf version.

SDF File Syntax

SDF file syntax in BNF notation with comments. Contributed by Kevin Cameron at Verilog Mixed Signal

Using Both VHDL and Verilog for Board-Level Simulation

Originally presented by Richard Munden at DesignCon99. You may also download the pdf version.

Board Level Simulation and the Free Model Foundry

Also in pdf.

Developing VITAL-Compliant VHDL Models (pdf)

by Arkadi Poliakov and Anatoli Sokhatski. Published in ISD MAgazine July 1999

A Comparison of Two VHDL Memory Modeling Techniques (pdf)

by Richard Munden. Published in the proceedings of the Mentor Users Group, February 2002

Building an Environment for VHDL Board-Level Simulation (pdf)

by Richard Munden. Published in the proceedings of the Intenational Cadence Users Group, September 2002

Free Models: What are They?; How are They Used?; How Can They be Free?

Verification Beyond the Chip (pdf)

How to add timing wrappers to RTL FPGA and ASIC models to enhance board-level verification.

by Richard Munden. Published in the proceeding of the Mentor Users Group 2004.

Instructions for using mk_sdf

Also recomended is ASIC & FPGA Verification: A Guide to Component Modeling written by Richard Munden, published by MKP and available from Amazon.com

A Comparison of VHDL and Verilog Behavioral Model Resource Usage

by Richard Munden. March 2007.

Tailoring Verification Models to Customer Needs

by Richard Munden and Stephan Rosner, Flash Memory Summit 2008.

Contact Richard Munden: munden@freemodelfoundry.com